| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 10 hours | aarch64: Treat operand Rt_IN_SYS_ALIASES as register number (PR 31919) | Jens Remus | 1 | -1/+1 |
| 13 hours | aarch64: Fix FEAT_B16B16 sve2 instruction constraints. | Srinath Parvathaneni | 2 | -33/+33 |
| 13 hours | arch64: Fix the wrong constraint used for sve2p1 instructions. | Srinath Parvathaneni | 1 | -13/+12 |
| 13 hours | aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands. | Srinath Parvathaneni | 5 | -209/+206 |
| 13 hours | aarch64: Fix sve2p1 extq instruction operands. | Srinath Parvathaneni | 5 | -28/+24 |
| 13 hours | aarch64: Fix sve2p1 dupq instruction operands. | Srinath Parvathaneni | 8 | -61/+13 |
| 34 hours | aarch64: Add SME FP8 multiplication instructions | Andrew Carlotti | 6 | -834/+1345 |
| 34 hours | aarch64: Add FP8 Neon and SVE multiplication instructions | Andrew Carlotti | 8 | -366/+877 |
| 35 hours | gas, aarch64: Add SME2 lutv2 extension | saurabh.jha@arm.com | 8 | -100/+208 |
| 5 days | x86: optimize {,V}PEXTR{D,Q} with immediate of 0 | Jan Beulich | 2 | -16/+16 |
| 5 days | x86: optimize left-shift-by-1 | Jan Beulich | 2 | -52/+52 |
| 5 days | x86/APX: fix disassembly of byte register operands | Jan Beulich | 1 | -0/+1 |
| 6 days | Revert "Remove LIBINTL_DEP" | Alan Modra | 3 | -2/+9 |
| 6 days | Remove LIBINTL_DEP | Alan Modra | 3 | -9/+2 |
| 7 days | x86: Remove the secondary encoding for ctest. | Cui, Lili | 2 | -570/+289 |
| 8 days | RISC-V: Add SiFive cease extension v1.0 | Hau Hsu | 1 | -0/+3 |
| 8 days | RISC-V: Support Zacas extension. | Gianluca Guida | 1 | -0/+26 |
| 8 days | x86: Fix typo in i386-dis-evex-mod.h | Cui, Lili | 1 | -2/+2 |
| 8 days | Remove %ME and used %NE for movbe. | Cui, Lili | 3 | -10/+14 |
| 8 days | Support APX CCMP and CTEST | Cui, Lili | 7 | -2233/+4165 |
| 11 days | aarch64: add SPMU system registers missed in f01ae0392ed | Matthieu Longo | 1 | -0/+79 |
| 13 days | aarch64: add Branch Record Buffer extension instructions | Claudio Bantaloukas | 6 | -2448/+2496 |
| 2024-06-11 | MIPS/opcodes: Add MIPS Allegrex DBREAK instruction | David Guillen Fandos | 1 | -1/+1 |
| 2024-06-11 | MIPS/opcodes: Exclude trap instructions for MIPS Allegrex | David Guillen Fandos | 1 | -30/+30 |
| 2024-06-10 | Revert "MIPS/Allegrex: Exclude trap instructions" | Maciej W. Rozycki | 1 | -30/+30 |
| 2024-06-10 | Revert "MIPS/Allegrex: Enable dbreak instruction" | Maciej W. Rozycki | 1 | -1/+1 |
| 2024-06-10 | MIPS/Allegrex: Enable dbreak instruction | David Guillen Fandos | 1 | -1/+1 |
| 2024-06-10 | MIPS/Allegrex: Exclude trap instructions | David Guillen Fandos | 1 | -30/+30 |
| 2024-06-10 | x86/APX: convert ZU to operand constraint | Jan Beulich | 4 | -4223/+4223 |
| 2024-06-10 | x86: disassembler macro for condition code | Jan Beulich | 3 | -281/+71 |
| 2024-06-10 | x86/APX: support extended SETcc form | Jan Beulich | 2 | -312/+555 |
| 2024-06-10 | x86/APX: add missing CPU requirement to imm+rm forms of <alu2> insns | Jan Beulich | 2 | -15/+15 |
| 2024-06-10 | autoupdate: regen after replacing obsolete macros | Matthieu Longo | 1 | -4/+2 |
| 2024-06-10 | autoupdate: add square brackets around arguments of AC_INIT | Matthieu Longo | 1 | -1/+1 |
| 2024-06-10 | autoupdate: replace obsolete macros AC_AIX, AC_MINIX, and AC_GNU_SOURCE | Matthieu Longo | 1 | -1/+0 |
| 2024-06-06 | opcodes/riscv: prevent future use of disassemble_info::fprintf_func | Andrew Burgess | 1 | -0/+5 |
| 2024-06-06 | opcodes/riscv: add styling support to print_reg_list | Andrew Burgess | 1 | -14/+37 |
| 2024-06-06 | RISC-V: Add support for Zvfbfwma extension | Xiao Zeng | 1 | -0/+4 |
| 2024-06-06 | RISC-V: Add support for Zvfbfmin extension | Xiao Zeng | 1 | -0/+4 |
| 2024-06-06 | RISC-V: Add support for Zfbfmin extension | Xiao Zeng | 1 | -0/+5 |
| 2024-06-05 | arm: remove disassembly support for the FPA co-processor | Richard Earnshaw | 1 | -196/+1 |
| 2024-06-05 | Fix illegal memory access when bfd_get_section_contents is called with a NULL... | Nick Clifton | 1 | -0/+7 |
| 2024-06-05 | RISC-V: Add support for XCVmem extension in CV32E40P | Mary Bennett | 1 | -0/+26 |
| 2024-06-05 | RISC-V: Add support for XCVbi extension in CV32E40P | Mary Bennett | 2 | -0/+8 |
| 2024-06-05 | RISC-V: Add support for XCVelw extension in CV32E40P | Mary Bennett | 1 | -0/+3 |
| 2024-05-29 | x86/Intel: warn about undue mnemonic suffixes | Jan Beulich | 4 | -5657/+5662 |
| 2024-05-28 | gas, aarch64: Add SVE2 lut extension | saurabh.jha@arm.com | 6 | -130/+252 |
| 2024-05-28 | gas, aarch64: Add AdvSIMD lut extension | saurabh.jha@arm.com | 10 | -362/+509 |
| 2024-05-28 | opcodes: add a .gitattributes file for aarch64 autogenerated file exceptions | Richard Earnshaw | 1 | -0/+3 |
| 2024-05-24 | x86: correct VCVT{,U}SI2SD | Jan Beulich | 2 | -16/+16 |
