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| author | Nick Clifton <nickc@redhat.com> | 2012-10-04 10:30:06 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2012-10-04 10:30:06 +0000 |
| commit | 04ee5257d646209723f3ed11afd838529fe6e3a7 (patch) | |
| tree | f5357fedde2ee5f38268ac75f9b65c381840229a /opcodes | |
| parent | 8936df7e3469f93027d754e0c3d545273d176495 (diff) | |
| download | gdb-04ee5257d646209723f3ed11afd838529fe6e3a7.zip gdb-04ee5257d646209723f3ed11afd838529fe6e3a7.tar.gz gdb-04ee5257d646209723f3ed11afd838529fe6e3a7.tar.bz2 | |
* v850-dis.c (disassemble): Place square parentheses around second
register operand of clr1, not1, set1 and tst1 instructions.
* config/tc-v850.c (v850_insert_operand): Use a static buffer for
the error message.
* gas/v850/v850e1.d: Fix expected disassembly of clr1, not1, set1
and tst1 insns.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 9 | ||||
| -rw-r--r-- | opcodes/v850-dis.c | 16 |
2 files changed, 21 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1400e05..214ea81 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2012-10-04 Nick Clifton <nickc@redhat.com> + + * v850-dis.c (disassemble): Place square parentheses around second + register operand of clr1, not1, set1 and tst1 instructions. + 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-mkopc.c: Support new option zEC12. @@ -11,8 +16,8 @@ 2012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com> - * i386-gen.c (cpu_flag_init): Add missing Cpu flags in - CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS + * i386-gen.c (cpu_flag_init): Add missing Cpu flags in + CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS and CPU_BTVER2_FLAGS. * i386-init.h: Regenerated. diff --git a/opcodes/v850-dis.c b/opcodes/v850-dis.c index 60b452b..5f9d87b 100644 --- a/opcodes/v850-dis.c +++ b/opcodes/v850-dis.c @@ -309,9 +309,11 @@ disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, uns We may need to output a trailing ']' if the last operand in an instruction is the register for a memory address. - The exception (and there's always an exception) is the + The exception (and there's always an exception) are the "jmp" insn which needs square brackets around it's only - register argument. */ + register argument, and the clr1/not1/set1/tst1 insns + which [...] around their second register argument. */ + prefix = ""; if (operand->flags & V850_OPERAND_BANG) { @@ -334,6 +336,16 @@ disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, uns info->fprintf_func (info->stream, "%s[", prefix); square = TRUE; } + else if (opnum == 2 + && ( op->opcode == 0x00e407e0 /* clr1 */ + || op->opcode == 0x00e207e0 /* not1 */ + || op->opcode == 0x00e007e0 /* set1 */ + || op->opcode == 0x00e607e0 /* tst1 */ + )) + { + info->fprintf_func (info->stream, ", %s[", prefix); + square = TRUE; + } else if (opnum > 1) info->fprintf_func (info->stream, ", %s", prefix); |