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path: root/opcodes/aarch64-opc.c
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2021-11-25Fix building the AArch64 assembler and disassembler when assertions are disab...Nick Clifton1-3/+8
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-0/+12
2021-11-17aarch64: [SME] Add new SME system registersPrzemyslaw Wirkus1-1/+11
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus1-4/+27
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus1-15/+67
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus1-0/+45
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus1-0/+15
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus1-0/+11
2021-04-19aarch64: New instructions for maintenance of GPT entries cached in a TLBPrzemyslaw Wirkus1-0/+5
2021-04-19aarch64: Add new data cache maintenance operationsPrzemyslaw Wirkus1-0/+2
2021-04-16aarch64: Define RME system registersPrzemyslaw Wirkus1-0/+4
2021-03-31Use bool in opcodesAlan Modra1-68/+68
2021-03-31Remove bfd_stdint.hAlan Modra1-1/+1
2021-03-29TRUE/FALSE simplificationAlan Modra1-30/+24
2021-03-12aarch64: Add few missing system registersPrzemyslaw Wirkus1-0/+10
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov1-4/+0
2021-01-08Treat the AArch64 register id_aa64mmfr2_el1 as a core system register.Nick Clifton1-1/+1
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-11-09aarch64: Update LS64 feature with system registerPrzemyslaw Wirkus1-0/+2
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-0/+1
2020-11-04aarch64: Update feature RAS system registersPrzemyslaw Wirkus1-0/+5
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus1-0/+4
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus1-0/+10
2020-10-22[PATCH][GAS][AArch64] Define BRBE system registersPrzemyslaw Wirkus1-0/+106
2020-10-22aarch64: Define CSRE system registersPrzemyslaw Wirkus1-0/+13
2020-09-28This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for t...Przemyslaw Wirkus1-0/+216
2020-09-28This patch introduces ETE (Embedded Trace Extension) system registers for the...Przemyslaw Wirkus1-0/+6
2020-09-28This patch introduces TRBE (Trace Buffer Extension) system registers for the ...Przemyslaw Wirkus1-0/+8
2020-09-08aarch64: Add support for Armv8-R system registersAlex Coplan1-9/+70
2020-08-12aarch64: Add support for MPAM system registersAlex Coplan1-0/+17
2020-08-10[aarch64] GAS doesn't validate the architecture version for any tlbi register...Przemyslaw Wirkus1-102/+96
2020-06-11[PATCH]: aarch64: Refactor representation of system registersAlex Coplan1-623/+448
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan1-0/+3
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das1-0/+3
2020-02-26Indent labelsAlan Modra1-1/+1
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-17ubsan: aarch64: left shift cannot be represented in type 'int64_t'Alan Modra1-12/+11
2019-11-11Arm64: fix build with old glibcJan Beulich1-10/+7
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-0/+2
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-0/+1
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv1-1/+6
2019-08-22[AArch64][gas] Update MTE system register encodingsKyrylo Tkachov1-10/+10
2019-07-23[AArch64] Add support for GMID_EL1 register for +memtagKyrylo Tkachov1-1/+3
2019-07-02[AArch64] Fix bogus MOVPRFX warning for GPR form of CPYRichard Sandiford1-5/+0
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-0/+2
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-0/+3
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-6/+12
2019-05-09[binutils][aarch64] New sve_size_sd2 iclass.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-0/+18
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-0/+4
generated by cgit v1.1 at 2024-11-25 22:16:17 +0000