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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-10-22 15:17:10 +0100 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-10-22 15:17:10 +0100 |
| commit | 5feaa09beca04312e51adc69766b0e4bfc181f99 (patch) | |
| tree | 3243079e3740ffe96513174725e13002a30ab7d8 /opcodes/aarch64-opc.c | |
| parent | bec0b9f6f2e74c799e382bcf5154ecab6bd77c74 (diff) | |
| download | gdb-5feaa09beca04312e51adc69766b0e4bfc181f99.zip gdb-5feaa09beca04312e51adc69766b0e4bfc181f99.tar.gz gdb-5feaa09beca04312e51adc69766b0e4bfc181f99.tar.bz2 | |
aarch64: Define CSRE system registers
This patch introduces CSRE (Call Stack Recorder Extension) system
registers.
Note: as this is register only extension we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).
CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size
of a Call stack record) instruction. This instruction will be added in
a following, separate patch. This change only adds CSRE system
registers.
gas/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* testsuite/gas/aarch64/csre-invalid.d: New test.
* testsuite/gas/aarch64/csre-invalid.l: New test.
* testsuite/gas/aarch64/csre-invalid.s: New test.
* testsuite/gas/aarch64/csre.d: New test.
* testsuite/gas/aarch64/csre.s: New test.
opcodes/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: New CSRE system registers defined.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 5c8d8ec..b97d055 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4541,6 +4541,19 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("trclar", CPENC (2,1,C7,C12,6), F_REG_WRITE), SR_CORE ("trcoslar", CPENC (2,1,C1,C0,4), F_REG_WRITE), + SR_CORE ("csrcr_el0", CPENC (2,3,C8,C0,0), 0), + SR_CORE ("csrptr_el0", CPENC (2,3,C8,C0,1), 0), + SR_CORE ("csridr_el0", CPENC (2,3,C8,C0,2), F_REG_READ), + SR_CORE ("csrptridx_el0", CPENC (2,3,C8,C0,3), F_REG_READ), + SR_CORE ("csrcr_el1", CPENC (2,0,C8,C0,0), 0), + SR_CORE ("csrcr_el12", CPENC (2,5,C8,C0,0), 0), + SR_CORE ("csrptr_el1", CPENC (2,0,C8,C0,1), 0), + SR_CORE ("csrptr_el12", CPENC (2,5,C8,C0,1), 0), + SR_CORE ("csrptridx_el1", CPENC (2,0,C8,C0,3), F_REG_READ), + SR_CORE ("csrcr_el2", CPENC (2,4,C8,C0,0), 0), + SR_CORE ("csrptr_el2", CPENC (2,4,C8,C0,1), 0), + SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3), F_REG_READ), + { 0, CPENC (0,0,0,0,0), 0, 0 } }; |