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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:26:53 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:27:42 +0000 |
| commit | d3de0860104b8bb8d496527fbb042c3b4c5c82dc (patch) | |
| tree | d639da6b0a9e7bc01d3331c170d7e15099299203 /opcodes/aarch64-opc.c | |
| parent | 8f1bfdb44894423680a6d56a0994dafb4b82efca (diff) | |
| download | gdb-d3de0860104b8bb8d496527fbb042c3b4c5c82dc.zip gdb-d3de0860104b8bb8d496527fbb042c3b4c5c82dc.tar.gz gdb-d3de0860104b8bb8d496527fbb042c3b4c5c82dc.tar.bz2 | |
aarch64: [SME] SVE2 instructions added to support SME
This patch is adding new SVE2 instructions added to support SME extension.
The following SVE2 instructions are added by the SME architecture:
* PSEL,
* REVD, SCLAMP and UCLAMP.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_pred_reg_with_index):
New parser.
(parse_operands): New parser.
* testsuite/gas/aarch64/sme-9-illegal.d: New test.
* testsuite/gas/aarch64/sme-9-illegal.l: New test.
* testsuite/gas/aarch64/sme-9-illegal.s: New test.
* testsuite/gas/aarch64/sme-9.d: New test.
* testsuite/gas/aarch64/sme-9.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operand
AARCH64_OPND_SME_PnT_Wm_imm.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index):
New inserter.
* aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index):
New extractor.
* aarch64-opc.c (aarch64_print_operand): Printout of
OPND_SME_PnT_Wm_imm.
* aarch64-opc.h (enum aarch64_field_kind): New bitfields
FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl.
* aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier.
(OP_SVE_QMQ): New qualifier.
(struct aarch64_opcode): New instructions PSEL, REVD,
SCLAMP and UCLAMP.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 923ddef..a37b3ff 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -332,6 +332,10 @@ const aarch64_field fields[] = { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */ { 13, 3 }, /* SME Pm second source scalable predicate register P0-P7. */ { 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */ + { 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */ + { 23, 1 }, /* SME_i1: immediate field, bit 23. */ + { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */ + { 18, 3 }, /* SME_tshl: immediate and qualifier field, bits [20:18]. */ { 11, 2 }, /* rotate1: FCMLA immediate rotate. */ { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */ { 12, 1 }, /* rotate3: FCADD immediate rotate. */ @@ -3473,6 +3477,14 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, snprintf (buf, size, "%s", opnd->reg.regno == 's' ? "sm" : "za"); break; + case AARCH64_OPND_SME_PnT_Wm_imm: + snprintf (buf, size, "p%d.%s[w%d, %d]", + opnd->za_tile_vector.regno, + aarch64_get_qualifier_name (opnd->qualifier), + opnd->za_tile_vector.index.regno, + opnd->za_tile_vector.index.imm); + break; + case AARCH64_OPND_CRn: case AARCH64_OPND_CRm: snprintf (buf, size, "C%" PRIi64, opnd->imm.value); |