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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 19:31:25 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 19:32:17 +0000 |
| commit | 7bb5f07c8aa5168009f1e7b6857a30f0ee5ad16a (patch) | |
| tree | e8a7449925ac32ef3a5ebf0db7276c348ca5bb8c /opcodes/aarch64-opc.c | |
| parent | 971eda734150ea9cdea47be259486c3a8d087037 (diff) | |
| download | gdb-7bb5f07c8aa5168009f1e7b6857a30f0ee5ad16a.zip gdb-7bb5f07c8aa5168009f1e7b6857a30f0ee5ad16a.tar.gz gdb-7bb5f07c8aa5168009f1e7b6857a30f0ee5ad16a.tar.bz2 | |
aarch64: [SME] Add MOV and MOVA instructions
This patch is adding new MOV (alias) and MOVA SME instruction.
gas/ChangeLog:
* config/tc-aarch64.c (enum sme_hv_slice): new enum.
(struct reloc_entry): Added ZAH and ZAV registers.
(parse_sme_immediate): Immediate parser.
(parse_sme_za_hv_tiles_operand): ZA tile parser.
(parse_sme_za_hv_tiles_operand_index): Index parser.
(parse_operands): Added ZA tile parser calls.
(REGNUMS): New macro. Regs with suffix.
(REGSET16S): New macro. 16 regs with suffix.
* testsuite/gas/aarch64/sme-2-illegal.d: New test.
* testsuite/gas/aarch64/sme-2-illegal.l: New test.
* testsuite/gas/aarch64/sme-2-illegal.s: New test.
* testsuite/gas/aarch64/sme-2.d: New test.
* testsuite/gas/aarch64/sme-2.s: New test.
* testsuite/gas/aarch64/sme-2a.d: New test.
* testsuite/gas/aarch64/sme-2a.s: New test.
* testsuite/gas/aarch64/sme-3-illegal.d: New test.
* testsuite/gas/aarch64/sme-3-illegal.l: New test.
* testsuite/gas/aarch64/sme-3-illegal.s: New test.
* testsuite/gas/aarch64/sme-3.d: New test.
* testsuite/gas/aarch64/sme-3.s: New test.
* testsuite/gas/aarch64/sme-3a.d: New test.
* testsuite/gas/aarch64/sme-3a.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New enums
AARCH64_OPND_SME_ZA_HV_idx_src and
AARCH64_OPND_SME_ZA_HV_idx_dest.
(struct aarch64_opnd_info): New ZA tile vector struct.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_sme_za_hv_tiles):
New inserter.
* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER):
New inserter ins_sme_za_hv_tiles.
* aarch64-dis.c (aarch64_ext_sme_za_hv_tiles):
New extractor.
* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR):
New extractor ext_sme_za_hv_tiles.
* aarch64-opc.c (aarch64_print_operand):
Handle SME_ZA_HV_idx_src and SME_ZA_HV_idx_dest.
* aarch64-opc.h (enum aarch64_field_kind): New enums
FLD_SME_size_10, FLD_SME_Q, FLD_SME_V and FLD_SME_Rv.
(struct aarch64_operand): Increase fields size to 5.
* aarch64-tbl.h (OP_SME_BHSDQ_PM_BHSDQ): New qualifiers
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 8ced8e0..b12bf3e 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -242,6 +242,7 @@ const aarch64_field fields[] = { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */ { 0, 4 }, /* imm4_2: in rmif instructions. */ { 10, 4 }, /* imm4_3: in adddg/subg instructions. */ + { 5, 4 }, /* imm4_5: in SME instructions. */ { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */ { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */ { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */ @@ -323,6 +324,10 @@ const aarch64_field fields[] = { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */ { 0, 2 }, /* SME ZAda tile ZA0-ZA3. */ { 0, 3 }, /* SME ZAda tile ZA0-ZA7. */ + { 22, 2 }, /* SME_size_10: size<1>, size<0> class field, [23:22]. */ + { 16, 1 }, /* SME_Q: Q class bit, bit 16. */ + { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */ + { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */ { 13, 3 }, /* SME Pm second source scalable predicate register P0-P7. */ { 11, 2 }, /* rotate1: FCMLA immediate rotate. */ { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */ @@ -3355,6 +3360,16 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, aarch64_get_qualifier_name (opnd->qualifier)); break; + case AARCH64_OPND_SME_ZA_HV_idx_src: + case AARCH64_OPND_SME_ZA_HV_idx_dest: + snprintf (buf, size, "za%d%c.%s[w%d, %d]", + opnd->za_tile_vector.regno, + opnd->za_tile_vector.v == 1 ? 'v' : 'h', + aarch64_get_qualifier_name (opnd->qualifier), + opnd->za_tile_vector.index.regno, + opnd->za_tile_vector.index.imm); + break; + case AARCH64_OPND_CRn: case AARCH64_OPND_CRm: snprintf (buf, size, "C%" PRIi64, opnd->imm.value); |