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2024-07-23Improve objdump's display of PE header information.Pali Roh?r2-3/+3
2024-07-20Add markers for 2.43 branch/releaseNick Clifton1-0/+4
2024-07-19MIPS/opcodes: Replace "y" microMIPS operand code with "x"Maciej W. Rozycki1-2/+2
2024-07-19MIPS/opcodes: Remove the regular MIPS "+t" operand codeYunQiang Su1-2/+1
2024-07-19MIPS/opcodes: Discard unused OP_SH, OP_MASK, and OP_OP macrosMaciej W. Rozycki1-454/+0
2024-07-19MIPS/opcodes: Correct documentation for R6 operand typesMaciej W. Rozycki1-7/+6
2024-07-18opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.cIndu Bhagat1-1/+2
2024-07-18include: opcodes: aarch64: define new subclassesIndu Bhagat1-1/+31
2024-07-12aarch64: Add support for sme2.1 zero instructions.Srinath Parvathaneni1-1/+10
2024-07-12aarch64: Add support for sme2.1 movaz instructions.Srinath Parvathaneni1-0/+1
2024-07-12aarch64: Add support for sme2.1 luti2 and luti4 instructions.Srinath Parvathaneni1-0/+1
2024-07-09include: sframe: update code comments around SFrame FRE stack offsetsIndu Bhagat1-10/+12
2024-07-09LTO: Properly check wrapper symbolH.J. Lu1-0/+3
2024-07-08aarch64: Add support for sve2p1 pmov instruction.srinath1-0/+8
2024-07-05aarch64: add STEP2 feature and its associated registersMatthieu Longo1-0/+3
2024-07-05aarch64: add SPMU2 feature and its associated registersMatthieu Longo1-0/+3
2024-07-05aarch64: add E3DSE feature and its associated registersMatthieu Longo1-1/+5
2024-06-28aarch64: Add support for Armv9.5-A architectureClaudio Bantaloukas1-0/+8
2024-06-28RISC-V: Add Zabha extension CAS instructions.Jiawei2-0/+7
2024-06-25aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.Srinath Parvathaneni1-3/+1
2024-06-25aarch64: Fix sve2p1 extq instruction operands.Srinath Parvathaneni1-1/+1
2024-06-25aarch64: Fix sve2p1 dupq instruction operands.Srinath Parvathaneni1-1/+1
2024-06-25aarch64: Enable mandatory feature bits for v9.4-A.Srinath Parvathaneni1-1/+2
2024-06-25gdb: LoongArch: Add support for hardware breakpointHui Li1-0/+2
2024-06-25gdb: LoongArch: Add support for hardware watchpointHui Li1-0/+2
2024-06-24aarch64: Add SME FP8 multiplication instructionsAndrew Carlotti1-0/+11
2024-06-24aarch64: Add FP8 Neon and SVE multiplication instructionsAndrew Carlotti1-6/+31
2024-06-24gas, aarch64: Add SME2 lutv2 extensionsaurabh.jha@arm.com1-0/+6
2024-06-23aarch64: Enable +cssc for armv8.9-aAndrew Carlotti1-0/+1
2024-06-18libctf, include: new functions for looking up enumeratorsNick Alcock1-0/+38
2024-06-18include: libctf: comment improvementsNick Alcock1-2/+5
2024-06-18libctf: prohibit addition of enums with overlapping enumerator constantsNick Alcock1-6/+7
2024-06-18include: fix libctf ECTF_NOENUMNAM error messageNick Alcock1-1/+1
2024-06-18RISC-V: Add SiFive cease extension v1.0Hau Hsu2-0/+4
2024-06-18RISC-V: Support Zacas extension.Gianluca Guida2-0/+12
2024-06-13Add --rosegment option to BFD linker to stop the '-z separate-code' from gene...Nick Clifton1-0/+3
2024-06-13MIPS/opcodes: Rework INSN_* flags into a consistent blockMaciej W. Rozycki1-28/+25
2024-06-13MIPS/opcodes: Update INSN_CHIP_MASK for INSN_ALLEGREXMaciej W. Rozycki1-1/+1
2024-06-12aarch64: add Branch Record Buffer extension instructionsClaudio Bantaloukas1-1/+6
2024-06-12RISC-V: Support S[sm]csrind extension csrs.Jiawei1-6/+40
2024-06-06RISC-V: Add support for Zvfbfwma extensionXiao Zeng2-0/+9
2024-06-06RISC-V: Add support for Zvfbfmin extensionXiao Zeng2-0/+9
2024-06-06RISC-V: Add support for Zfbfmin extensionXiao Zeng2-0/+9
2024-06-05arm: remove disassembly support for the FPA co-processorRichard Earnshaw1-4/+3
2024-06-05arm: remove options to select the FPARichard Earnshaw1-3/+0
2024-06-05arm: rename FPU_ARCH_VFP to FPU_ARCH_SOFTVFPRichard Earnshaw1-1/+1
2024-06-05RISC-V: Add support for XCVmem extension in CV32E40PMary Bennett2-0/+50
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett2-0/+9
2024-06-05RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett2-0/+4
2024-05-28gas, aarch64: Add SVE2 lut extensionsaurabh.jha@arm.com1-0/+3
generated by cgit v1.1 at 2024-12-23 11:42:16 +0000