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| author | Gianluca Guida <gianluca@rivosinc.com> | 2023-05-31 17:28:56 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-18 14:35:50 +0800 |
| commit | 88729e96162f0293177d2324fc8dc6cd78aac793 (patch) | |
| tree | 9bb7bbe7394dbc46add1801b711f30d2a7680c7d /include | |
| parent | 0915235d341841ac7f13bd3136991c19b4a6746b (diff) | |
| download | gdb-88729e96162f0293177d2324fc8dc6cd78aac793.zip gdb-88729e96162f0293177d2324fc8dc6cd78aac793.tar.gz gdb-88729e96162f0293177d2324fc8dc6cd78aac793.tar.bz2 | |
RISC-V: Support Zacas extension.
https://github.com/riscvarchive/riscv-zacas/releases/tag/v1.0
The Zacas extension introduce compare-and-swap instructions to operate
on 32-bit, 64-bit and 128-bit (RV64 only) data values.
It introduces three new instructions:
- amocas.w (32-bit CAS)
- amocas.d (64-bit CAS)
- amocas.q (128-bit CAS, RV64 only)
Like other AMOs in the A extension, Zacas instructions have '.aq',
'.rl' and '.aqrl' variations.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): 'A' implied by 'Zacas'.
(riscv_supported_std_z_ext): Add 'Zacas' extension.
(riscv_multi_subset_supports, riscv_multi_subset_supports_ext):
Handle INSN_CLASS_ZACAS case.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Updated.
* testsuite/gas/riscv/zacas-32.d: New test (RV32).
* testsuite/gas/riscv/zacas-fail-32.d: Likewise.
* testsuite/gas/riscv/zacas-64.d: New test (RV64).
* testsuite/gas/riscv/zacas-fail-64.d: Likewise.
* testsuite/gas/riscv/zacas.s: New test source.
* testsuite/gas/riscv/zacas-fail.s: Likewise.
* testsuite/gas/riscv/zacas-fail-32.l: New file.
* testsuite/gas/riscv/zacas-fail-64.l: Likewise.
include/ChangeLog:
* include/opcode/riscv.h (INSN_CLASS_ZACAS): New definition.
* include/opcode/riscv-opc.h (MATCH_AMOCAS_W, MASK_AMOCAS_W)
(MATCH_AMOCAS_D, MASK_AMOCAS_D, MATCH_AMOCAS_Q, MASK_AMOCAS_Q):
Likewise.
(amocas_w, amocas_d, amocas_q): Declare instructions.
opcodes/ChangeLog:
* riscv-opc.c (match_rs2_rd_even): New function.
(amocas_w, amocas_d, amocas_q, amocas_w.aq)
(amocas_d.aq, amocas_q.aq, amocas_w.rl, amocas_d.rl, amocas_q.rl)
(amocas_w.aqrl, amocas_d.aqrl, amocas_q.aqrl): Add instructions.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 11 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 |
2 files changed, 12 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 511895e..f87822a 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2360,6 +2360,13 @@ #define MASK_C_NTL_S1 0xffff #define MATCH_C_NTL_ALL 0x9016 #define MASK_C_NTL_ALL 0xffff +/* Zacas instructions. */ +#define MATCH_AMOCAS_W 0x2800202f +#define MASK_AMOCAS_W 0xf800707f +#define MATCH_AMOCAS_D 0x2800302f +#define MASK_AMOCAS_D 0xf800707f +#define MATCH_AMOCAS_Q 0x2800402f +#define MASK_AMOCAS_Q 0xf800707f /* Zawrs instructions. */ #define MATCH_WRS_NTO 0x00d00073 #define MASK_WRS_NTO 0xffffffff @@ -3998,6 +4005,10 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1) DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL) DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1) DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) +/* Zacas instructions. */ +DECLARE_INSN(amocas_w, MATCH_AMOCAS_W, MASK_AMOCAS_W) +DECLARE_INSN(amocas_d, MATCH_AMOCAS_D, MASK_AMOCAS_D) +DECLARE_INSN(amocas_q, MATCH_AMOCAS_Q, MASK_AMOCAS_Q) /* Zawrs instructions. */ DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 33df56d..20bfdb1 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -492,6 +492,7 @@ enum riscv_insn_class INSN_CLASS_ZICBOP, INSN_CLASS_ZICBOZ, INSN_CLASS_ZABHA, + INSN_CLASS_ZACAS, INSN_CLASS_H, INSN_CLASS_XCVMAC, INSN_CLASS_XCVALU, |