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| author | Matthieu Longo <matthieu.longo@arm.com> | 2024-06-19 20:10:22 +0100 |
|---|---|---|
| committer | Matthieu Longo <matthieu.longo@arm.com> | 2024-07-05 15:39:28 +0100 |
| commit | 27e411ef5db28b6cf591749ff81d3c5c8193f6cf (patch) | |
| tree | 781899e992b7ce6bb051d345393018b96f255ae6 /include | |
| parent | a15809c010f32e1d72379babbd230c82e3f46901 (diff) | |
| download | gdb-27e411ef5db28b6cf591749ff81d3c5c8193f6cf.zip gdb-27e411ef5db28b6cf591749ff81d3c5c8193f6cf.tar.gz gdb-27e411ef5db28b6cf591749ff81d3c5c8193f6cf.tar.bz2 | |
aarch64: add SPMU2 feature and its associated registers
AArch64 defines new registers for the feature spmu2 (System Performance
Monitors Extension version 2). spmu2 is an Armv9.5-A feature.
This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 17c4ee9..4dc3019 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -222,6 +222,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_PMUv3_ICNTR, /* System Performance Monitors Extension */ AARCH64_FEATURE_SPMU, + /* System Performance Monitors Extension version 2 */ + AARCH64_FEATURE_SPMU2, /* Performance Monitors Synchronous-Exception-Based Event Extension. */ AARCH64_FEATURE_SEBEP, /* SVE2.1 and SME2.1 non-widening BFloat16 instructions. */ @@ -370,6 +372,7 @@ enum aarch64_feature_bit { | AARCH64_FEATBIT (X, LUT) \ | AARCH64_FEATBIT (X, FAMINMAX)\ | AARCH64_FEATBIT (X, E3DSE) \ + | AARCH64_FEATBIT (X, SPMU2) \ ) /* Architectures are the sum of the base and extensions. */ |