include: opcodes: aarch64: define new subclasses

The existing iclass information tells us the general shape and purpose
of the instructions.  In some cases, however, we need to further disect
the iclass on the basis of other finer-grain information.  E.g., for the
purpose of SCFI, we need to know whether a given insn with iclass of
ldst_* is a load or a store.  Similarly, whether a particular arithmetic
insn is an add or sub or mov, etc.

This patch defines new flags to demarcate the insns.  Also provide an
access function for subclass lookup.

Later, we will enforce (in aarch64-gen.c) that if an iclass has at least
one instruction with a non-zero subclass, all instructions of the iclass
must have a non-zero subclass information.  If none of the defined
subclasses are applicable (or not required for SCFI purposes),
F_SUBCLASS_OTHER can be used for such instructions.

include/
        * opcode/aarch64.h (F_SUBCLASS): New flag.
        (F_SUBCLASS_OTHER): Likewise.
        (F_LDST_LOAD): Likewise.
        (F_LDST_STORE): Likewise.
        (F_ARITH_ADD): Likewise.
        (F_ARITH_SUB): Likewise.
        (F_ARITH_MOV): Likewise.
        (F_BRANCH_CALL): Likewise.
        (F_BRANCH_RET): Likewise.
	(F_DP_TAG_ONLY): Likewise.
        (aarch64_opcode_subclass_p): New definition.

1 files changed, 31 insertions, 1 deletions

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 1b01931..df07d3b 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1390,7 +1390,27 @@ extern const aarch64_opcode aarch64_opcode_table[];
 /* This instruction need VGx2 or VGx4 mandatorily in the operand passed to
    assembler.  */
 #define F_VG_REQ (1ULL << 36)
-/* Next bit is 37.  */
+
+/* 4-bit flag field to indicate subclass of instructions.
+   Note the overlap between the set of subclass flags in each logical category
+   (F_LDST_*, F_ARITH_*, F_BRANCH_* etc.);  The usage of flags as
+   iclass-specific enums is intentional.  */
+#define F_SUBCLASS (15ULL << 37)
+
+#define F_LDST_LOAD (1ULL << 37)
+#define F_LDST_STORE (2ULL << 37)
+/* Subclasses to denote add, sub and mov insns.  */
+#define F_ARITH_ADD (1ULL << 37)
+#define F_ARITH_SUB (2ULL << 37)
+#define F_ARITH_MOV (3ULL << 37)
+/* Subclasses to denote call and ret insns.  */
+#define F_BRANCH_CALL (1ULL << 37)
+#define F_BRANCH_RET (2ULL << 37)
+/* Subclass to denote that only tag update is involved.  */
+#define F_DP_TAG_ONLY (1ULL << 37)
+
+#define F_SUBCLASS_OTHER (F_SUBCLASS)
+/* Next bit is 41.  */
 
 /* Instruction constraints.  */
 /* This instruction has a predication constraint on the instruction at PC+4.  */
@@ -1429,6 +1449,16 @@ pseudo_opcode_p (const aarch64_opcode *opcode)
   return (opcode->flags & F_PSEUDO) != 0lu;
 }
 
+/* Whether the opcode has the specific subclass flag.
+   N.B. The overlap between F_LDST_*, F_ARITH_*, and F_BRANCH_* etc. subclass
+   flags means that the callers of this function have the responsibility of
+   checking for the flags appropriate for the specific iclass.  */
+static inline bool
+aarch64_opcode_subclass_p (const aarch64_opcode *opcode, uint64_t flag)
+{
+  return ((opcode->flags & F_SUBCLASS) == flag);
+}
+
 /* Deal with two possible scenarios: If F_OP_PAIR_OPT not set, as is the case
    by default, F_OPDn_OPT must equal IDX + 1, else F_OPDn_OPT must be in range
    [IDX, IDX + 1].  */