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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-07-08 16:36:44 +0100 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2024-07-12 15:41:56 +0100 |
| commit | 7bdb051fd62ca70aa2cf549441b7728d20a3a631 (patch) | |
| tree | 2285ed9d79fd35d898fb1fae79f365372eafd146 /include | |
| parent | 6ab366f2643d13507e53e85684dc5b5a5e14b54b (diff) | |
| download | gdb-7bdb051fd62ca70aa2cf549441b7728d20a3a631.zip gdb-7bdb051fd62ca70aa2cf549441b7728d20a3a631.tar.gz gdb-7bdb051fd62ca70aa2cf549441b7728d20a3a631.tar.bz2 | |
aarch64: Add support for sme2.1 zero instructions.
This patch adds support for following sme2.1 zero instructions and
the spec is available here [1].
1. ZERO (single-vector).
2. ZERO (double-vector).
3. ZERO (quad-vector).
The VECTOR GROUP symbols VGx2 and VGx4 are optional for the assembler
for most of the sme and sve instructions. But for few of the sme2.1
zero instruction variants VECTOR GROUP symbols VGx2 and VGx4 are mandatory.
To address this a bit "F_VG_REQ" is introduced in this patch, on setting
F_VG_REQ bit in flags of aarch64_opcode forces the assembler to accept
instruction operand only having VECTOR GROUP symbols.
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 5a2b99d..1b01931 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1387,7 +1387,10 @@ extern const aarch64_opcode aarch64_opcode_table[]; #define F_OPD_SIZE (1ULL << 34) /* RCPC3 instruction has the field of 'size'. */ #define F_RCPC3_SIZE (1ULL << 35) -/* Next bit is 36. */ +/* This instruction need VGx2 or VGx4 mandatorily in the operand passed to + assembler. */ +#define F_VG_REQ (1ULL << 36) +/* Next bit is 37. */ /* Instruction constraints. */ /* This instruction has a predication constraint on the instruction at PC+4. */ @@ -1451,6 +1454,12 @@ get_opcode_dependent_value (const aarch64_opcode *opcode) } static inline bool +get_opcode_dependent_vg_status (const aarch64_opcode *opcode) +{ + return (opcode->flags >> 36) & 0x1; +} + +static inline bool opcode_has_special_coder (const aarch64_opcode *opcode) { return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T |