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| author | Maciej W. Rozycki <macro@redhat.com> | 2024-07-19 19:01:53 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@redhat.com> | 2024-07-19 19:01:53 +0100 |
| commit | b39807cc93bb85c9654b39a5c17f9d8de940429e (patch) | |
| tree | 4fab871b2a3b2b8fb5c53d034a1713dc7909bc6e /include | |
| parent | 0ffc7246996b40cd189694fca7b297913a9ea000 (diff) | |
| download | gdb-b39807cc93bb85c9654b39a5c17f9d8de940429e.zip gdb-b39807cc93bb85c9654b39a5c17f9d8de940429e.tar.gz gdb-b39807cc93bb85c9654b39a5c17f9d8de940429e.tar.bz2 | |
MIPS/opcodes: Replace "y" microMIPS operand code with "x"
Replace the "y" microMIPS operand code, used with ALNV.PS only, with "x"
so as to make "y" available for microMIPS MT use.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/mips.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 1e4b3e2..67849ff 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1798,7 +1798,7 @@ extern const int bfd_mips16_num_opcodes; (MICROMIPSOP_*_RS) "w" 5-bit same register used as both target and destination (MICROMIPSOP_*_RT) - "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) + "x" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) "z" must be zero register "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) @@ -1908,7 +1908,7 @@ extern const int bfd_mips16_num_opcodes; "12345678 0" "<>(),+-.@\^|~" "ABCDEFGHI KLMN RST V " - "abcd fghijklmnopqrstuvw yz" + "abcd fghijklmnopqrstuvwx z" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: |