riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2 days	RISC-V: Fix incorrect code gen for scalar signed SAT_TRUNC [PR117688]	Pan Li	7	-0/+58
2 days	RISC-V: Fix incorrect code gen for scalar signed SAT_SUB [PR117688]	Pan Li	5	-0/+45
2 days	RISC-V: Fix incorrect code gen for scalar signed SAT_ADD [PR117688]	Pan Li	5	-0/+51
4 days	RISC-V: testsuite: Fix reduc-8.c and reduc-9.c	Robin Dapp	2	-2/+0
4 days	RISC-V: testsuite: Fix gather_load_64-12-zvbb.c	Robin Dapp	1	-1/+2
5 days	RISC-V: Make FRM as global register [PR118103]	Pan Li	2	-0/+77
10 days	Revert "[PATCH 2/2] RISC-V:Add intrinsic cases for the CMOs extensions"	Jeff Law	2	-116/+0
10 days	RISC-V: Enable and adjust the testsuite for XTheadVector.	Jin Ma	9	-59/+79
11 days	[PR target/116256] Adjust expected output in a couple testcases	Jeff Law	2	-2/+2
11 days	[PR target/114442] Add reservations for all insn types to xiangshan-nanhu model	Jeff Law	1	-0/+3
11 days	RISC-V: Correct the mode that is causing the program to fail for XTheadCondMov	Jin Ma	1	-0/+12
13 days	[RISC-V][PR target/116308] Fix generation of initial RTL for atomics	Jeff Law	1	-0/+9
13 days	RISC-V: Disable RV64-only crc testcases for RV32	Bohan Lei	2	-6/+4
13 days	[PR target/118357] RISC-V: Disable fusing vsetvl instructions by VSETVL_VTYPE...	Jin Ma	1	-0/+13
2025-01-17	RISC-V: Add -fcf-protection=[full\|branch\|return] to enable zicfiss, zicfilp.	Monk Chiang	4	-4/+4
2025-01-17	RISC-V: Add Zicfilp ISA extension.	Monk Chiang	2	-0/+21
2025-01-17	RISC-V: Add Zicfiss ISA extension.	Monk Chiang	2	-0/+51
2025-01-16	RISC-V: Update Xsfvqmacc and Xsfvfnrclip's testcases	Liao Shihua	10	-1/+255
2025-01-15	RISC-V: Fix code gen for reduction with length 0 [PR118182]	Kito Cheng	2	-0/+55
2025-01-14	[RISC-V][PR target/118170] Add HF div/sqrt reservation	Anton Blanchard	1	-0/+9
2025-01-14	[PR rtl-optimization/109592] Simplify nested shifts	Richard Sandiford	2	-4/+13
2025-01-14	RISC-V: Fix vsetvl compatibility predicate [PR118154].	Robin Dapp	2	-0/+54
2025-01-14	match: Keep conditional in simplification to constant [PR118140].	Robin Dapp	1	-0/+29
2025-01-13	RISC-V: Disallow negative step for interleaving [PR117682]	Robin Dapp	1	-0/+15
2025-01-13	RISC-V: testsuite: Skip test with -flto	Robin Dapp	8	-14/+16
2025-01-13	RISC-V: Remove zba check in bitwise and ashift reassociation [PR 115921]	Xi Ruoyao	1	-0/+9
2025-01-13	RISC-V: Fix the result error caused by not updating ratio when using "use_max...	Jin Ma	1	-0/+14
2025-01-13	RISC-V: Fix program logic errors caused by data truncation on 32-bit host for...	Jin Ma	1	-0/+15
2025-01-13	[PR rtl-optimization/107455] Eliminate unnecessary constant load	Jeff Law	2	-0/+86
2025-01-07	RISC-V: vector absolute difference expander [PR117722]	Vineet Gupta	1	-0/+23
2025-01-07	Prefer scalar_int_mode if the size - 1 is equal to UNITS_PER_WORD.	Tsung Chun Lin	2	-1/+18
2025-01-07	Fix testsuite expectations for RVV after recent change	Jeff Law	2	-3/+3
2025-01-07	testsuite: RISC-V: Skip tests providing -march for ILP32E/ILP64E ABIs	Dimitar Dimitrov	489	-489/+489
2025-01-07	testsuite: RISC-V: Skip tests using -mcpu= for ILP32E/ILP64E ABIs	Dimitar Dimitrov	2	-2/+2
2025-01-07	testsuite: RISC-V: Skip V and Zvbb tests for ILP32E/ILP64E ABIs	Dimitar Dimitrov	22	-22/+22
2025-01-07	RISC-V: Add missing dg-runtest to run the testcase under gcc.target/riscv/rvv/	Tsung Chun Lin	1	-0/+2
2025-01-06	RISC-V: Move fortran testcase to gfortran.target	Kito Cheng	3	-117/+0
2025-01-02	Update copyright years.	Jakub Jelinek	4	-4/+4
2025-01-02	RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4	xuli	26	-16/+738
2024-12-30	[RISC-V][PR target/106544] Avoid ICEs due to bogus asms	Jeff Law	1	-0/+6
2024-12-30	[RISC-V][PR target/118122] Fix modes in recently added risc-v pattern	Jeff Law	1	-0/+12
2024-12-29	[RISC-V] [V2] [PR target/116715] Remove bogus bitmanip pattern	Jeff Law	1	-0/+18
2024-12-29	[PR target/116720] Fix test for valid mempair operands	Jeff Law	1	-0/+12
2024-12-21	[RISC-V][PR middle-end/118084] Fix brev based reflection code	Jeff Law	1	-0/+13
2024-12-20	avoid trying to set block in barriers [PR113506]	Alexandre Oliva	1	-0/+15
2024-12-20	RISC-V: Refine strided load/store testcase dump check to tree optimized	Pan Li	11	-63/+63
2024-12-19	RISC-V: Adjust the strided store testcases check times on options	Pan Li	3	-3/+6
2024-12-19	RISC-V: Make vector strided store alias all other memories	Pan Li	1	-0/+24
2024-12-17	[PATCH] RISC-V: optimization on checking certain bits set ((x & mask) == val)	Oliver Kozul	1	-0/+16
2024-12-17	[PATCH v2 2/2] RISC-V: Add Tenstorrent Ascalon 8 wide architecture	Anton Blanchard	1	-0/+76