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2024-12-17RISC-V: Add new constraint R for register even-odd pairsKito Cheng1-0/+23
2024-12-17RISC-V: Implment N modifier for printing the register number rather than the ...Kito Cheng3-0/+50
2024-12-17RISC-V: Add cr and cf constraintKito Cheng3-0/+41
2024-12-16RISC-V: Fix compress shuffle pattern [PR117383].Robin Dapp2-1/+49
2024-12-16RISC-V: Increase cost for vec_construct [PR118019].Robin Dapp1-0/+52
2024-12-13RISC-V: Improve slide1up pattern.Robin Dapp1-1/+1
2024-12-13RISC-V: Add even/odd vec_perm_const pattern.Robin Dapp2-0/+190
2024-12-13RISC-V: Add interleave pattern.Robin Dapp2-0/+191
2024-12-13RISC-V: Add slide to perm_const strategies.Robin Dapp2-0/+473
2024-12-13RISC-V: Emit vector shift pattern for const_vector [PR117353].Robin Dapp1-0/+29
2024-12-13RISC-V: Make vector strided load alias all other memoriesPan Li1-0/+24
2024-12-10RISC-V: Refine signed vector SAT_SUB testcase dump check to tree optimizedPan Li16-48/+48
2024-12-10RISC-V: Refine signed vector SAT_TRUNC testcase dump check to tree optimizedPan Li48-141/+141
2024-12-10RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimizedPan Li16-48/+48
2024-12-10RISC-V: Refine unsigned vector SAT_TRUNC testcase dump check to tree optimizedPan Li24-48/+48
2024-12-10RISC-V: Refine unsigned vector SAT_SUB testcase dump check to tree optimizedPan Li48-100/+100
2024-12-10RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimizedPan Li63-127/+127
2024-12-09[committed] RISC-V testsuite changes to test clmul expansion of CRCsMariam Arutunian42-0/+419
2024-12-09RISC-V: Refine signed SAT_TRUNC testcase dump check to tree optimizedPan Li48-96/+96
2024-12-09RISC-V: Refine signed SAT_SUB testcase dump check to tree optimizedPan Li16-32/+32
2024-12-09RISC-V: Refine signed SAT_ADD testcase dump check to tree optimizedPan Li23-46/+46
2024-12-09RISC-V: Refine unsigned SAT_TRUNC testcase dump check to tree optimizedPan Li24-48/+48
2024-12-09RISC-V: Refine unsigned SAT_SUB testcase dump check to tree optimizedPan Li100-200/+200
2024-12-09RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimizedPan Li100-200/+200
2024-12-09RISC-V: Fix incorrect optimization options passing to partialPan Li1-1/+1
2024-12-09RISC-V: Refactor the testcases for rvv binop and cmpPan Li6-6/+70
2024-12-09RISC-V: Fix incorrect optimization options passing to binop and cmpPan Li1-2/+2
2024-12-06RISC-V: Refactor the testcases for bswap16-0Pan Li1-1/+1
2024-12-06RISC-V: Fix incorrect optimization options passing to convert and unopPan Li1-2/+2
2024-12-04sched1: parameterize pressure scheduling spilling aggressiveness [PR/114729]Vineet Gupta2-0/+34
2024-12-03RISC-V: Fix test target selectorEdwin Lu2-2/+2
2024-12-03RISC-V: Fix incorrect optimization options passing to reduc and ternopPan Li1-2/+2
2024-12-03RISC-V: Fix incorrect optimization options passing to cond and builtinPan Li1-2/+2
2024-12-02Add trailing newlines where neededJakub Jelinek6-6/+6
2024-12-02RISC-V: Add intrinsics testcases for SiFive Xsfvfnrclipxfqf extensions.yulong2-0/+1211
2024-12-02RISC-V: Fix incorrect optimization options passing to widdenPan Li1-1/+1
2024-12-02RISC-V: Fix RVV strided load/store testcases failurePan Li11-59/+231
2024-11-30[PATCH v3] zero_extend(not) -> xor optimization [PR112398]Alexey Merzlyakov1-0/+14
2024-11-29[PATCH v7 03/12] RISC-V: Add CRC expander to generate faster CRC.Mariam Arutunian2-0/+87
2024-11-29RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/dod extensions.yulong9-0/+1706
2024-11-26[PATCH] testsuite:RISC-V:Modify the char string.yulong1-1/+1
2024-11-26RISC-V: Refactor the testcases for RVV gather/scatterPan Li5-8/+30
2024-11-26RISC-V: Fix incorrect optimization options passing to gather/scatterPan Li1-1/+1
2024-11-25RISC-V: Ensure vtype for full-register moves [PR117544].Robin Dapp2-0/+15
2024-11-25RISC-V: Minimal support for svvptc extension.Dongyan Chen1-0/+5
2024-11-24RISC-V: Refine the vector stride load/store testcasesPan Li11-44/+44
2024-11-24RISC-V: Refactor the test files for all other vector SAT ALUPan Li131-1145/+574
2024-11-24RISC-V: Rearrange the test files for all other vector SAT ALU [NFC]Pan Li136-1896/+0
2024-11-24RISC-V: Refactor the testcases for vector SAT_TRUNCPan Li48-72/+72
2024-11-24RISC-V: Rearrange the test files for vector SAT_TRUNC [NFC]Pan Li50-0/+698