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riscv
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Commit message (
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Author
Files
Lines
2024-12-17
RISC-V: Add new constraint R for register even-odd pairs
Kito Cheng
1
-0
/
+23
2024-12-17
RISC-V: Implment N modifier for printing the register number rather than the ...
Kito Cheng
3
-0
/
+50
2024-12-17
RISC-V: Add cr and cf constraint
Kito Cheng
3
-0
/
+41
2024-12-16
RISC-V: Fix compress shuffle pattern [PR117383].
Robin Dapp
2
-1
/
+49
2024-12-16
RISC-V: Increase cost for vec_construct [PR118019].
Robin Dapp
1
-0
/
+52
2024-12-13
RISC-V: Improve slide1up pattern.
Robin Dapp
1
-1
/
+1
2024-12-13
RISC-V: Add even/odd vec_perm_const pattern.
Robin Dapp
2
-0
/
+190
2024-12-13
RISC-V: Add interleave pattern.
Robin Dapp
2
-0
/
+191
2024-12-13
RISC-V: Add slide to perm_const strategies.
Robin Dapp
2
-0
/
+473
2024-12-13
RISC-V: Emit vector shift pattern for const_vector [PR117353].
Robin Dapp
1
-0
/
+29
2024-12-13
RISC-V: Make vector strided load alias all other memories
Pan Li
1
-0
/
+24
2024-12-10
RISC-V: Refine signed vector SAT_SUB testcase dump check to tree optimized
Pan Li
16
-48
/
+48
2024-12-10
RISC-V: Refine signed vector SAT_TRUNC testcase dump check to tree optimized
Pan Li
48
-141
/
+141
2024-12-10
RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimized
Pan Li
16
-48
/
+48
2024-12-10
RISC-V: Refine unsigned vector SAT_TRUNC testcase dump check to tree optimized
Pan Li
24
-48
/
+48
2024-12-10
RISC-V: Refine unsigned vector SAT_SUB testcase dump check to tree optimized
Pan Li
48
-100
/
+100
2024-12-10
RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimized
Pan Li
63
-127
/
+127
2024-12-09
[committed] RISC-V testsuite changes to test clmul expansion of CRCs
Mariam Arutunian
42
-0
/
+419
2024-12-09
RISC-V: Refine signed SAT_TRUNC testcase dump check to tree optimized
Pan Li
48
-96
/
+96
2024-12-09
RISC-V: Refine signed SAT_SUB testcase dump check to tree optimized
Pan Li
16
-32
/
+32
2024-12-09
RISC-V: Refine signed SAT_ADD testcase dump check to tree optimized
Pan Li
23
-46
/
+46
2024-12-09
RISC-V: Refine unsigned SAT_TRUNC testcase dump check to tree optimized
Pan Li
24
-48
/
+48
2024-12-09
RISC-V: Refine unsigned SAT_SUB testcase dump check to tree optimized
Pan Li
100
-200
/
+200
2024-12-09
RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimized
Pan Li
100
-200
/
+200
2024-12-09
RISC-V: Fix incorrect optimization options passing to partial
Pan Li
1
-1
/
+1
2024-12-09
RISC-V: Refactor the testcases for rvv binop and cmp
Pan Li
6
-6
/
+70
2024-12-09
RISC-V: Fix incorrect optimization options passing to binop and cmp
Pan Li
1
-2
/
+2
2024-12-06
RISC-V: Refactor the testcases for bswap16-0
Pan Li
1
-1
/
+1
2024-12-06
RISC-V: Fix incorrect optimization options passing to convert and unop
Pan Li
1
-2
/
+2
2024-12-04
sched1: parameterize pressure scheduling spilling aggressiveness [PR/114729]
Vineet Gupta
2
-0
/
+34
2024-12-03
RISC-V: Fix test target selector
Edwin Lu
2
-2
/
+2
2024-12-03
RISC-V: Fix incorrect optimization options passing to reduc and ternop
Pan Li
1
-2
/
+2
2024-12-03
RISC-V: Fix incorrect optimization options passing to cond and builtin
Pan Li
1
-2
/
+2
2024-12-02
Add trailing newlines where needed
Jakub Jelinek
6
-6
/
+6
2024-12-02
RISC-V: Add intrinsics testcases for SiFive Xsfvfnrclipxfqf extensions.
yulong
2
-0
/
+1211
2024-12-02
RISC-V: Fix incorrect optimization options passing to widden
Pan Li
1
-1
/
+1
2024-12-02
RISC-V: Fix RVV strided load/store testcases failure
Pan Li
11
-59
/
+231
2024-11-30
[PATCH v3] zero_extend(not) -> xor optimization [PR112398]
Alexey Merzlyakov
1
-0
/
+14
2024-11-29
[PATCH v7 03/12] RISC-V: Add CRC expander to generate faster CRC.
Mariam Arutunian
2
-0
/
+87
2024-11-29
RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/dod extensions.
yulong
9
-0
/
+1706
2024-11-26
[PATCH] testsuite:RISC-V:Modify the char string.
yulong
1
-1
/
+1
2024-11-26
RISC-V: Refactor the testcases for RVV gather/scatter
Pan Li
5
-8
/
+30
2024-11-26
RISC-V: Fix incorrect optimization options passing to gather/scatter
Pan Li
1
-1
/
+1
2024-11-25
RISC-V: Ensure vtype for full-register moves [PR117544].
Robin Dapp
2
-0
/
+15
2024-11-25
RISC-V: Minimal support for svvptc extension.
Dongyan Chen
1
-0
/
+5
2024-11-24
RISC-V: Refine the vector stride load/store testcases
Pan Li
11
-44
/
+44
2024-11-24
RISC-V: Refactor the test files for all other vector SAT ALU
Pan Li
131
-1145
/
+574
2024-11-24
RISC-V: Rearrange the test files for all other vector SAT ALU [NFC]
Pan Li
136
-1896
/
+0
2024-11-24
RISC-V: Refactor the testcases for vector SAT_TRUNC
Pan Li
48
-72
/
+72
2024-11-24
RISC-V: Rearrange the test files for vector SAT_TRUNC [NFC]
Pan Li
50
-0
/
+698
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