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| author | Robin Dapp <rdapp@ventanamicro.com> | 2025-01-13 16:26:24 -0700 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2025-01-13 16:26:24 -0700 |
| commit | 1f6453684696b1c18899cbbecd4bd5ed4ae22476 (patch) | |
| tree | dd3f9a1ed6ac9256a8f531aee1370990e12c4fc5 /gcc/testsuite/gcc.target/riscv | |
| parent | 9a4bb95a4e68b6f90a16f337b0b4cdb9af957ab1 (diff) | |
| download | gcc-1f6453684696b1c18899cbbecd4bd5ed4ae22476.zip gcc-1f6453684696b1c18899cbbecd4bd5ed4ae22476.tar.gz gcc-1f6453684696b1c18899cbbecd4bd5ed4ae22476.tar.bz2 | |
RISC-V: testsuite: Skip test with -flto
Hi,
the zbb-rol-ror and stack_save_restore tests use the -fno-lto option and
scan the final assembly. For an invocation like -flto ... -fno-lto the
output file we scan is still something like
zbb-rol-ror-09.ltrans0.ltrans.s.
Therefore skip the tests when "-flto" is present. This gets rid
of a few UNRESOLVED tests.
Regtested on rv64gcv_zvl512b. Going to push if the CI agrees.
Regards
Robin
gcc/testsuite/ChangeLog:
* gcc.target/riscv/stack_save_restore_1.c: Skip for -flto.
* gcc.target/riscv/stack_save_restore_2.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-04.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-05.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-06.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-07.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-08.c: Ditto.
* gcc.target/riscv/zbb-rol-ror-09.c: Ditto.
Diffstat (limited to 'gcc/testsuite/gcc.target/riscv')
8 files changed, 16 insertions, 14 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c b/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c index d8b0668..e0a7c68 100644 --- a/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c +++ b/gcc/testsuite/gcc.target/riscv/stack_save_restore_1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64imafc -mabi=lp64f -msave-restore -O2 -fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops -fno-lto" } */ +/* { dg-options "-march=rv64imafc -mabi=lp64f -msave-restore -O2 -fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ /* { dg-final { check-function-bodies "**" "" } } */ char my_getchar(); diff --git a/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c b/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c index 5f03892..aadeaa5 100644 --- a/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c +++ b/gcc/testsuite/gcc.target/riscv/stack_save_restore_2.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32imafc -mabi=ilp32f -msave-restore -O2 -fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops -fno-lto" } */ +/* { dg-options "-march=rv32imafc -mabi=ilp32f -msave-restore -O2 -fno-schedule-insns -fno-schedule-insns2 -fno-unroll-loops -fno-peel-loops" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ /* { dg-final { check-function-bodies "**" "" } } */ char my_getchar(); diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c index 28350e5..b413b10 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ -/* { dg-skip-if "" { *-*-* } { "-g" } } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */ /* { dg-final { check-function-bodies "**" "" } } */ /* { dg-final { scan-assembler-not {\mand} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c index cc44653..179477e 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */ -/* { dg-skip-if "" { *-*-* } { "-g" } } */ +/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */ /* { dg-final { check-function-bodies "**" "" } } */ /* { dg-final { scan-assembler-not {\mand} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c index 7a98a57..b5f0b8b 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ -/* { dg-skip-if "" { *-*-* } { "-g" } } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */ /* { dg-final { check-function-bodies "**" "" } } */ /* { dg-final { scan-assembler-not {\mand} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c index a08a9eb..0372306 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ -/* { dg-skip-if "" { *-*-* } { "-g" } } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */ /* { dg-final { check-function-bodies "**" "" } } */ /* { dg-final { scan-assembler-not {\mand} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c index bf19b76..b3864e7 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-08.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ -/* { dg-skip-if "" { *-*-* } { "-g" } } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */ /* { dg-final { check-function-bodies "**" "" } } */ /* { dg-final { scan-assembler-not {\mand} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c index 5c4b9f5..121dca9 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-09.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */ -/* { dg-skip-if "" { *-*-* } { "-g" } } */ +/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto" } } */ /* { dg-final { check-function-bodies "**" "" } } */ /* { dg-final { scan-assembler-not {\mand} } } */ |