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| author | Pan Li <pan2.li@intel.com> | 2024-12-19 08:58:20 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2024-12-19 15:59:21 +0800 |
| commit | 46194b912780452e80c1ef9867cbcff1050231a2 (patch) | |
| tree | b0a1adc9478112f4b65d3642dd8718fb2d91201f /gcc/testsuite/gcc.target/riscv | |
| parent | 87f97ffba93a2de17eca3927af901e3b3a103df7 (diff) | |
| download | gcc-46194b912780452e80c1ef9867cbcff1050231a2.zip gcc-46194b912780452e80c1ef9867cbcff1050231a2.tar.gz gcc-46194b912780452e80c1ef9867cbcff1050231a2.tar.bz2 | |
RISC-V: Make vector strided store alias all other memories
Almost the same as the RVV strided load, the vector strided store
doesn't involve the (mem:BLK (scratch)) to alias all other memories.
It will make the alias analysis only consider the base address of
strided store.
PR target/118075
gcc/ChangeLog:
* config/riscv/vector.md: Add the (mem:BLK (scratch)) as the
lhs of strided store define insn.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr118075-run-1.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc/testsuite/gcc.target/riscv')
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/pr118075-run-1.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr118075-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118075-run-1.c new file mode 100644 index 0000000..120573a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr118075-run-1.c @@ -0,0 +1,24 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl256b -mrvv-vector-bits=zvl" } */ + +int a; +int b[14]; +char c[14][14]; + +int main() { + for (long f = 0; f < 14; ++f) + for (long g = 0; g < 4; ++g) + c[f][g] = 1; + + for (short f = 0; f < 12; f += 1) + c[f][f] = b[f]; + + for (long f = 0; f < 4; ++f) + for (long g = 0; g < 14; ++g) + a ^= c[f][g]; + + if (a != 0) + __builtin_abort (); + + return 0; +} |