The fuzzer tripped over a risc-v target issue in the expansion of CRCs. In particular we want to use brev instruction to improve the reflection code. In the case where the item to be reflected is smaller than a word we would end up triggering an ICE due to mode mismatching since the expansion code asks for the operation in word_mode. I was briefly confused by the multiple calls into this code, but we have to reflect multiple values and those calls may be reflecting different sized items. So seeing one in SI, then another in QI is sensible. The fix is pretty simple. In theory the item being reflected should always be word_size or smaller. So an assertion is added to verify that. If the item's size is smaller than a word, we can use a paradoxical subreg. The logical right shift after the brev should zero out any extraneous bits. It's unclear why we're passing a pointer to an RTX in this code. I left that as-is, but we can simplify the code a little bit by doing the dereference early and using the dereferenced value. PR middle-end/118084 gcc/ * config/riscv/riscv.cc (generate_reflecting_code_using_brev): Handle sub-word sized objects correctly. gcc/testsuite/ * gcc.target/riscv/pr118084.c: New test.