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| author | Jin Ma <jinma@linux.alibaba.com> | 2025-01-20 09:29:30 -0700 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2025-01-20 09:30:01 -0700 |
| commit | 9d869296f095a02c37d3721f546ce99663e5417c (patch) | |
| tree | ccc6c9d374645bbf14e1699d204bc322b4d68e63 /gcc/testsuite/gcc.target/riscv | |
| parent | 0fe35e9b93a286de78dd5b80d8d58e9ef0591f03 (diff) | |
| download | gcc-9d869296f095a02c37d3721f546ce99663e5417c.zip gcc-9d869296f095a02c37d3721f546ce99663e5417c.tar.gz gcc-9d869296f095a02c37d3721f546ce99663e5417c.tar.bz2 | |
RISC-V: Correct the mode that is causing the program to fail for XTheadCondMov
For XTheadCondMov, the bit width of rs2 should always be XLEN-sized, otherwise
the program logic will be wrong.
Reference form
https://github.com/XUANTIE-RV/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
Synopsis
Move if equal zero.
Mnemonic
th.mveqz rd, rs1, rs2
Description
This instruction moves the content of register rs1 into rd if the content of rs2 is 0x0.
Otherwise, the value of rd does not change.
Operation
if (reg[rs2] == 0x0)
reg[rd] := reg[rs1]
gcc/ChangeLog:
* config/riscv/thead.md (*th_cond_mov<GPR:mode><GPR2:mode>):
Change GPR2 to X.
(*th_cond_mov<GPR:mode>): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadcondmov-bug.c: New test.
Diffstat (limited to 'gcc/testsuite/gcc.target/riscv')
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/xtheadcondmov-bug.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-bug.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-bug.c new file mode 100644 index 0000000..01cec62 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-bug.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64d -O2" } */ + +long long int +foo (long long int x, long long int y) +{ + if (((int) x | (int) y) != 0) + return 6; + return x + y; +} + +/* { dg-final { scan-assembler-times {\msext\.w\M} 1 } } */ |