aboutsummaryrefslogtreecommitdiff
path: root/gcc/config/aarch64/predicates.md
AgeCommit message (Expand)AuthorFilesLines
2021-04-27aarch64: Fix UB in the compiler [PR100200]Jakub Jelinek1-2/+2
2021-03-08aarch64: Fix PR99437 - tighten shift predicates for narrowing shift patternsKyrylo Tkachov1-0/+16
2021-01-04Update copyright years.Jakub Jelinek1-1/+1
2020-12-22arm&aarch64: subdivide the type attribute "alu_shfit_imm"Qian Jianhua1-0/+2
2020-09-07aarch64: Remove redundant mult patternsAlex Coplan1-15/+0
2020-07-09aarch64: Mitigate SLS for BLR instructionMatthew Malcomson1-1/+2
2020-01-17[AArch64] [SVE] Implement svld1ro intrinsic.Matthew Malcomson1-0/+16
2020-01-09[AArch64] Pass a mode to some SVE immediate queriesRichard Sandiford1-4/+4
2020-01-01Update copyright years.Jakub Jelinek1-1/+1
2019-11-19[AArch64] Implement Armv8.5-A memory tagging (MTE) intrinsicsDennis Zhang1-0/+14
2019-11-18Add optabs for accelerating RAW and WAR alias checksRichard Sandiford1-0/+5
2019-10-29[AArch64] Add support for arm_sve.hRichard Sandiford1-3/+86
2019-10-29[AArch64] Handle scalars in cmp and shift immediate queriesRichard Sandiford1-2/+2
2019-08-19[AArch64] Use scvtf fbits option where appropriateJoel Hutton1-0/+4
2019-08-15[AArch64] Rework SVE INC/DEC handlingRichard Sandiford1-4/+13
2019-08-15[AArch64] Use SVE binary immediate instructions for conditional arithmeticRichard Sandiford1-2/+6
2019-08-14[AArch64] Use SVE UXT[BHW] as a form of predicated ANDRichard Sandiford1-0/+19
2019-08-14[AArch64] Make more use of SVE conditional constant movesRichard Sandiford1-1/+6
2019-08-14[AArch64] Add support for SVE F{MAX,MIN}NM immediateRichard Sandiford1-0/+9
2019-08-14[AArch64] Add support for SVE [SU]{MAX,MIN} immediateRichard Sandiford1-3/+15
2019-08-14[AArch64] Add support for SVE CNOTRichard Sandiford1-0/+4
2019-08-14[AArch64] Use SVE ADR to optimise shift-add sequencesRichard Sandiford1-0/+12
2019-08-14[AArch64] Add a "GP strictness" operand to SVE FP unspecsRichard Sandiford1-0/+5
2019-08-14[AArch64] Rework SVE PTEST patternsRichard Sandiford1-0/+5
2019-08-13[AArch64] Improve SVE constant movesRichard Sandiford1-0/+10
2019-08-13[AArch64] Add a "y" constraint for V0-V7Richard Sandiford1-2/+1
2019-08-07[AArch64] Fix INSR for zero floatsRichard Sandiford1-2/+2
2019-05-12Accept code attributes as rtx codes in .md filesRichard Sandiford1-6/+0
2019-02-22Handle stack pointer with SUBS/ADDS instructions.Matthew Malcomson1-0/+4
2019-02-07[AArch64] Change representation of SABD in RTLKyrylo Tkachov1-0/+6
2019-01-16__builtin_<add/sub>_overflow issues on AArch64 (redux)Richard Earnshaw1-6/+20
2019-01-01Update copyright years.Jakub Jelinek1-1/+1
2018-10-31aarch64: Improve cas generationRichard Henderson1-0/+12
2018-09-19[AARCH64] Use STLUR for atomic_storeMatthew Malcomson1-0/+30
2018-07-19[AArch64][PATCH 2/2] PR target/83009: Relax strict address checking for storeAndre Vieira1-1/+1
2018-07-19[AArch64][PATCH 1/2] Fix addressing printing of LDP/STPAndre Vieira1-2/+3
2018-07-02aarch64: Add movprfx patterns alternativesRichard Henderson1-0/+3
2018-05-30Reverting r260635Andre Vieira1-1/+1
2018-05-24PR target/83009: Relax strict address checking for store pair lanesAndre Vieira1-1/+1
2018-05-22[AArch64] Merge stores of D-register values with different modesJackson Woodruff1-0/+4
2018-03-07re PR target/84565 (ICE in extract_insn, at recog.c:2304 on aarch64)Jakub Jelinek1-1/+1
2018-02-01[AArch64] Handle SVE subregs that are effectively REVsRichard Sandiford1-0/+4
2018-01-17[AArch64] PR82964: Fix 128-bit immediate ICEsWilco Dijkstra1-7/+6
2018-01-13Add support for SVE gather loadsRichard Sandiford1-0/+8
2018-01-13[AArch64] SVE load/store_lanes supportRichard Sandiford1-0/+8
2018-01-13[AArch64] Add SVE supportRichard Sandiford1-22/+176
2018-01-11aarch64-modes.def (V2HF): New VECTOR_MODE.Michael Collison1-0/+12
2018-01-03[AArch64] Rewrite aarch64_simd_valid_immediateRichard Sandiford1-4/+4
2018-01-03Update copyright years.Jakub Jelinek1-1/+1
2017-12-21[AArch64] Tweak aarch64_classify_address interfaceRichard Sandiford1-4/+4
generated by cgit v1.1 at 2025-01-16 12:09:19 +0000