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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-08-13 09:49:36 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-08-13 09:49:36 +0000 |
| commit | 163b1f6ab2950553e1cc1b39a6b49293b3390e46 (patch) | |
| tree | ccad3fb1c6f81d456a008c3a5f1234025aa95a3b /gcc/config/aarch64/predicates.md | |
| parent | 3e2751ce5591dc8f3b5f4ffd3dacf0fb8f789395 (diff) | |
| download | gcc-163b1f6ab2950553e1cc1b39a6b49293b3390e46.zip gcc-163b1f6ab2950553e1cc1b39a6b49293b3390e46.tar.gz gcc-163b1f6ab2950553e1cc1b39a6b49293b3390e46.tar.bz2 | |
[AArch64] Add a "y" constraint for V0-V7
Some indexed SVE FCMLA operations have a 3-bit register field that
requires one of Z0-Z7. This patch adds a public "y" constraint for that.
The patch also documents "x", which is again intended to be a public
constraint.
2019-08-13 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* doc/md.texi: Document the x and y constraints for AArch64.
* config/aarch64/aarch64.h (FP_LO8_REGNUM_P): New macro.
(FP_LO8_REGS): New reg_class.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add an entry for FP_LO8_REGS.
* config/aarch64/aarch64.c (aarch64_hard_regno_nregs)
(aarch64_regno_regclass, aarch64_class_max_nregs): Handle FP_LO8_REGS.
* config/aarch64/predicates.md (aarch64_simd_register): Use
FP_REGNUM_P instead of checking the classes manually.
* config/aarch64/constraints.md (y): New constraint.
gcc/testsuite/
* gcc.target/aarch64/asm-x-constraint-1.c: New test.
* gcc.target/aarch64/asm-y-constraint-1.c: Likewise.
From-SVN: r274367
Diffstat (limited to 'gcc/config/aarch64/predicates.md')
| -rw-r--r-- | gcc/config/aarch64/predicates.md | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 2cd0b87..3a8b507 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -53,8 +53,7 @@ (define_predicate "aarch64_simd_register" (and (match_code "reg") - (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS") - (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS")))) + (match_test "FP_REGNUM_P (REGNO (op))"))) (define_predicate "aarch64_reg_or_zero" (and (match_code "reg,subreg,const_int,const_double") |