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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-10-31 09:42:39 +0000 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2018-10-31 02:42:39 -0700 |
| commit | d400fda3a8c3330f77eb9d51874f5482d3819a9f (patch) | |
| tree | 08710f98cae30de9be33b762f03784aa1a42c07b /gcc/config/aarch64/predicates.md | |
| parent | 77f33f44baf24c22848197aa80962c003dd7b3e2 (diff) | |
| download | gcc-d400fda3a8c3330f77eb9d51874f5482d3819a9f.zip gcc-d400fda3a8c3330f77eb9d51874f5482d3819a9f.tar.gz gcc-d400fda3a8c3330f77eb9d51874f5482d3819a9f.tar.bz2 | |
aarch64: Improve cas generation
Do not zero-extend the input to the cas for subword operations;
instead, use the appropriate zero-extending compare insns.
Correct the predicates and constraints for immediate expected operand.
* config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): New.
(aarch64_split_compare_and_swap): Use it.
(aarch64_expand_compare_and_swap): Likewise. Remove convert_modes;
test oldval against the proper predicate.
* config/aarch64/atomics.md (@atomic_compare_and_swap<ALLI>):
Use nonmemory_operand for expected.
(cas_short_expected_pred): New.
(@aarch64_compare_and_swap<SHORT>): Use it; use "rn" not "rI" to match.
(@aarch64_compare_and_swap<GPI>): Use "rn" not "rI" for expected.
* config/aarch64/predicates.md (aarch64_plushi_immediate): New.
(aarch64_plushi_operand): New.
From-SVN: r265657
Diffstat (limited to 'gcc/config/aarch64/predicates.md')
| -rw-r--r-- | gcc/config/aarch64/predicates.md | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 5b08b03..4c75eff 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -114,6 +114,18 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "aarch64_plus_immediate"))) +(define_predicate "aarch64_plushi_immediate" + (match_code "const_int") +{ + HOST_WIDE_INT val = INTVAL (op); + /* The HImode value must be zero-extendable to an SImode plus_operand. */ + return ((val & 0xfff) == val || sext_hwi (val & 0xf000, 16) == val); +}) + +(define_predicate "aarch64_plushi_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "aarch64_plushi_immediate"))) + (define_predicate "aarch64_pluslong_immediate" (and (match_code "const_int") (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)"))) |