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2022-09-09RISC-V: Suppress build warningsKito Cheng1-18/+18
2022-09-05RISC-V: Support Zmmul extensionLiaoShihua1-0/+4
2022-09-02RISC-V: Implement TARGET_COMPUTE_MULTILIBKito Cheng1-0/+377
2022-09-02Add TARGET_COMPUTE_MULTILIB hook to override multi-lib result.Kito Cheng3-0/+51
2022-08-29s390: Add -munroll-only-small-loops.Robin Dapp1-0/+5
2022-08-26cr16: remove obsoleted portMartin Liska1-27/+0
2022-08-16RISC-V: Support zfh and zfhmin extensionKito Cheng1-0/+8
2022-08-15xtensa: Turn on -fsplit-wide-types-early by defaultTakayuki 'January June' Suwa1-0/+2
2022-07-26LoongArch: Support split symbol.Lulu Cheng1-0/+1
2022-07-03loongarch: use -mno-check-zero-division as the default for optimized codeXi Ruoyao1-3/+0
2022-07-01i386: Add AVX512BW to AVX512F in MASK_ISA2Haochen Jiang1-3/+2
2022-06-25Remove long deprecated tilegx and tilepro portsJeff Law2-112/+0
2022-06-13x86: Require AVX for F16C and VAESH.J. Lu1-4/+4
2022-05-24RISC-V: Add mininal support for Zicbo[mzp]ShiYulong1-0/+8
2022-05-23[x86_64]: Zhaoxin lujiazui enablementMayshao3-1/+64
2022-05-23RISC-V: Fix canonical extension order (K and J)Tsukasa OI1-1/+1
2022-05-16Use more ARRAY_SIZE.Martin Liska1-2/+1
2022-05-11i386: simplify cpu_feature handlingMartin Liska1-22/+28
2022-04-12IBM zSystems: Add support for z16 as CPU name.Andreas Krebbel1-2/+2
2022-03-29LoongArch Port: gcc buildchenglulu1-0/+43
2022-03-21x86: Disable SSE in ISA2 for -mgeneral-regs-onlyH.J. Lu1-1/+1
2022-03-21x86: Properly check FEATURE_AESKLEH.J. Lu1-2/+2
2022-03-21RISC-V: Implement misc macro for vector extensions.Kito Cheng1-8/+8
2022-03-16RISC-V: Add version info for zk, zkn and zksKito Cheng1-0/+4
2022-03-16RISC-V: Handle combine extension in canonical ordering.LiaoShihua1-0/+56
2022-03-04rs6000: Allow -mlong-double-64 after -mabi={ibm,ieee}longdouble [PR104208, PR...Peter Bergner1-0/+10
2022-02-09i386: -mno-xsave should disable all relevant ISA flags [PR104462]Uros Bizjak1-1/+2
2022-01-24properly disable -fsplit-stack on non-glibc targets [PR104170]Jakub Jelinek2-4/+6
2022-01-24RISC-V: Do not emit zcisr and zifencei if i-ext is 2.0Kito Cheng1-2/+12
2022-01-21x86: Properly disable -fsplit-stack support on non-glibc targetsH.J. Lu1-6/+11
2022-01-21Disable -fsplit-stack support on non-glibc targetsSören Tempel1-4/+10
2022-01-18RISC-V: Fix use-after-free error in `parse_multiletter_ext'Maciej W. Rozycki1-1/+1
2022-01-18riscv: fix -Wformat-diag errors.Martin Liska1-8/+8
2022-01-17Change references of .c files to .cc filesMartin Liska4-5/+5
2022-01-17Rename .c files to .cc files.Martin Liska50-0/+0
2022-01-14ARM: fix -Wformat= errorMartin Liska1-1/+1
2022-01-13Fix -Wformat-diag for ARM target.Martin Liska1-6/+6
2022-01-07RISC-V: Minimal support of vector extensionsKito Cheng1-0/+86
2022-01-07RISC-V: Allow extension name contain digitKito Cheng1-4/+38
2022-01-04x86: Update model value for Alderlake and RocketlakeCui,Lili1-0/+2
2022-01-03Update copyright years.Jakub Jelinek57-57/+57
2021-12-04RISC-V: Add implied defines of Zk, Zkn and ZksSiYu Wu1-1/+15
2021-12-04RISC-V: Add option defines for Scalar CryptographySiYu Wu1-0/+22
2021-11-11RISC-V: Fix wrong zifencei handling in riscv_subset_list::to_stringKito Cheng1-1/+1
2021-11-10[PR/target 102957] Allow Z*-ext extension with only 2 char.Kito Cheng1-1/+0
2021-10-25RISC-V: Minimal support of bitmanip extensionKito Cheng1-0/+10
2021-10-05Mark argument as unusedJan-Benedict Glaw1-1/+2
2021-09-21arm: pass architecture extensions to assembler if supportedRichard Earnshaw1-0/+10
2021-09-17x86: Update -mtune=tremontH.J. Lu1-1/+1
2021-09-13i386: support micro-levels in target{,_clone} attrs [PR101696]Martin Liska3-0/+61