[x86_64]: Zhaoxin lujiazui enablement

This patch fix Zhaoxin CPU vendor ID detection problem and add zhaoxin
"lujiazui" processor support.  Currently gcc can't recognize Zhaoxin CPU
(vendor ID "CentaurHauls" and "Shanghai") if user use -march=native option,
which is confusing for users.  This patch enables -march=native in zhaoxin
family 7th processor and -march/-mtune=lujiazui, costs and tunning are set
according to the characteristics of the processor.
We add a new md file to describe lujiazui pipeline.

Testing:
Bootstrap is ok, and no regressions for i386/x86-64 testsuite.

Background:
Related Zhaoxin linux kernel patch can be found at:
https://lore.kernel.org/lkml/01042674b2f741b2aed1f797359bdffb@zhaoxin.com/

Related Zhaoxin glibc patch can be found at:
https://sourceware.org/git/?p=glibc.git;a=commit;h=32ac0b988466785d6e3cc1dffc364bb26fc63193

gcc/ChangeLog:

	* common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Detect
	the specific type of Zhaoxin CPU, and return Zhaoxin CPU name.
	(cpu_indicator_init): Handle Zhaoxin processors.
	* common/config/i386/i386-common.cc: Add lujiazui.
	* common/config/i386/i386-cpuinfo.h (enum processor_vendor): Add
	VENDOR_ZHAOXIN.
	(enum processor_types): Add ZHAOXIN_FAM7H.
	(enum processor_subtypes): Add ZHAOXIN_FAM7H_LUJIAZUI.
	* config.gcc: Add lujiazui.
	* config/i386/cpuid.h (signature_SHANGHAI_ebx): Add
	Signatures for zhaoxin
	(signature_SHANGHAI_ecx): Ditto.
	(signature_SHANGHAI_edx): Ditto.
	* config/i386/driver-i386.cc (host_detect_local_cpu): Let
	-march=native recognize lujiazui processors.
	* config/i386/i386-c.cc (ix86_target_macros_internal): Add lujiazui.
	* config/i386/i386-options.cc (m_LUJIAZUI): New_definition.
	* config/i386/i386.h (enum processor_type): Ditto.
	* config/i386/i386.md: Add lujiazui.
	* config/i386/x86-tune-costs.h (struct processor_costs): Add
	lujiazui costs.
	* config/i386/x86-tune-sched.cc (ix86_issue_rate): Add lujiazui.
	(ix86_adjust_cost): Ditto.
	* config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Add lujiazui Tunnings.
	(X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto.
	(X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto.
	(X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto.
	(X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto.
	(X86_TUNE_MOVX): Ditto.
	(X86_TUNE_MEMORY_MISMATCH_STALL): Ditto.
	(X86_TUNE_FUSE_CMP_AND_BRANCH_32): Ditto.
	(X86_TUNE_FUSE_CMP_AND_BRANCH_64): Ditto.
	(X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS): Ditto.
	(X86_TUNE_FUSE_ALU_AND_BRANCH): Ditto.
	(X86_TUNE_ACCUMULATE_OUTGOING_ARGS): Ditto.
	(X86_TUNE_USE_LEAVE): Ditto.
	(X86_TUNE_PUSH_MEMORY): Ditto.
	(X86_TUNE_LCP_STALL): Ditto.
	(X86_TUNE_USE_INCDEC): Ditto.
	(X86_TUNE_INTEGER_DFMODE_MOVES): Ditto.
	(X86_TUNE_OPT_AGU): Ditto.
	(X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Ditto.
	(X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto.
	(X86_TUNE_USE_SAHF): Ditto.
	(X86_TUNE_USE_BT): Ditto.
	(X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Ditto.
	(X86_TUNE_ONE_IF_CONV_INSN): Ditto.
	(X86_TUNE_AVOID_MFENCE): Ditto.
	(X86_TUNE_EXPAND_ABS): Ditto.
	(X86_TUNE_USE_SIMODE_FIOP): Ditto.
	(X86_TUNE_USE_FFREEP): Ditto.
	(X86_TUNE_EXT_80387_CONSTANTS): Ditto.
	(X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto.
	(X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto.
	(X86_TUNE_SSE_TYPELESS_STORES): Ditto.
	(X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto.
	* doc/extend.texi: Add details about lujiazui.
	* doc/invoke.texi: Add details about lujiazui.
	* config/i386/lujiazui.md: Introduce lujiazui cpu and include new md file.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/funcspec-56.inc: Test -arch=lujiauzi and -tune=lujiazui.
	* g++.target/i386/mv32.C: Ditto.

Signed-off-by: mayshao <mayshao-oc@zhaoxin.com>

3 files changed, 64 insertions, 1 deletions

diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 6d6171f..adc02bc 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -526,6 +526,39 @@ get_intel_cpu (struct __processor_model *cpu_model,
   return cpu;
 }
 
+/* Get the specific type of ZHAOXIN CPU and return ZHAOXIN CPU name.
+   Return NULL for unknown ZHAOXIN CPU.  */
+
+static inline const char *
+get_zhaoxin_cpu (struct __processor_model *cpu_model,
+		struct __processor_model2 *cpu_model2,
+		unsigned int *cpu_features2)
+{
+  const char *cpu = NULL;
+  unsigned int family = cpu_model2->__cpu_family;
+  unsigned int model = cpu_model2->__cpu_model;
+
+  switch (family)
+    {
+    /* ZHAOXIN family 7h.  */
+    case 0x07:
+      cpu_model->__cpu_type = ZHAOXIN_FAM7H;
+      if (model == 0x3b)
+	{
+	cpu = "lujiazui";
+	CHECK___builtin_cpu_is ("lujiazui");
+	cpu_model->__cpu_features[0] &= ~(1U <<(FEATURE_AVX & 31));
+	cpu_features2[0] &= ~(1U <<((FEATURE_F16C - 32) & 31));
+	cpu_model->__cpu_subtype = ZHAOXIN_FAM7H_LUJIAZUI;
+	}
+      break;
+    default:
+      break;
+    }
+
+  return cpu;
+}
+
 /* ECX and EDX are output of CPUID at level one.  */
 static inline void
 get_available_features (struct __processor_model *cpu_model,
@@ -936,8 +969,27 @@ cpu_indicator_init (struct __processor_model *cpu_model,
       get_amd_cpu (cpu_model, cpu_model2, cpu_features2);
       cpu_model->__cpu_vendor = VENDOR_AMD;
     }
-  else if (vendor == signature_CENTAUR_ebx)
+  else if (vendor == signature_CENTAUR_ebx && family < 0x07)
     cpu_model->__cpu_vendor = VENDOR_CENTAUR;
+  else if (vendor == signature_SHANGHAI_ebx
+		|| vendor == signature_CENTAUR_ebx)
+    {
+      /* Adjust model and family for ZHAOXIN CPUS.  */
+      if (family == 0x07)
+	{
+	  model += extended_model;
+	}
+
+      cpu_model2->__cpu_family = family;
+      cpu_model2->__cpu_model = model;
+
+      /* Find available features.  */
+      get_available_features (cpu_model, cpu_model2, cpu_features2,
+				  ecx, edx);
+      /* Get CPU type.  */
+      get_zhaoxin_cpu (cpu_model, cpu_model2,cpu_features2);
+      cpu_model->__cpu_vendor = VENDOR_ZHAOXIN;
+    }
   else if (vendor == signature_CYRIX_ebx)
     cpu_model->__cpu_vendor = VENDOR_CYRIX;
   else if (vendor == signature_NSC_ebx)
diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index 07fdd04..cb878163 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -1817,6 +1817,7 @@ const char *const processor_names[] =
   "alderlake",
   "rocketlake",
   "intel",
+  "lujiazui",
   "geode",
   "k6",
   "athlon",
@@ -1995,6 +1996,13 @@ const pta processor_alias_table[] =
   {"nano-x4", PROCESSOR_K8, CPU_K8,
     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
       | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
+  {"lujiazui", PROCESSOR_LUJIAZUI, CPU_LUJIAZUI,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+	| PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_BMI | PTA_BMI2
+	| PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
+	| PTA_RDRND | PTA_MOVBE | PTA_ADX | PTA_RDSEED | PTA_POPCNT,
+	M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), P_NONE},
   {"k8", PROCESSOR_K8, CPU_K8,
     PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
       | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
index 3f6d201..643fbd9 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -29,6 +29,7 @@ enum processor_vendor
 {
   VENDOR_INTEL = 1,
   VENDOR_AMD,
+  VENDOR_ZHAOXIN,
   VENDOR_OTHER,
   VENDOR_CENTAUR,
   VENDOR_CYRIX,
@@ -56,6 +57,7 @@ enum processor_types
   INTEL_GOLDMONT_PLUS,
   INTEL_TREMONT,
   AMDFAM19H,
+  ZHAOXIN_FAM7H,
   CPU_TYPE_MAX,
   BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX
 };
@@ -89,6 +91,7 @@ enum processor_subtypes
   INTEL_COREI7_ALDERLAKE,
   AMDFAM19H_ZNVER3,
   INTEL_COREI7_ROCKETLAKE,
+  ZHAOXIN_FAM7H_LUJIAZUI,
   CPU_SUBTYPE_MAX
 };