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| author | Kito Cheng <kito.cheng@sifive.com> | 2022-03-21 16:16:14 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-03-21 16:17:12 +0800 |
| commit | 5177634148aab7a7b193eaa9b8c73ce00a38c481 (patch) | |
| tree | f107ae1dbc9b8e1440f46197a50f5ca90647bd88 /gcc/common | |
| parent | e767da23de12ceb1bf3aece4dae0ae20bf605b04 (diff) | |
| download | gcc-5177634148aab7a7b193eaa9b8c73ce00a38c481.zip gcc-5177634148aab7a7b193eaa9b8c73ce00a38c481.tar.gz gcc-5177634148aab7a7b193eaa9b8c73ce00a38c481.tar.bz2 | |
RISC-V: Implement misc macro for vector extensions.
See also:
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
Update flag name and mask name.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Define
misc macro for vector extensions.
* config/riscv/riscv-opts.h (MASK_VECTOR_EEW_32): Rename to ...
(MASK_VECTOR_ELEN_32): ... this.
(MASK_VECTOR_EEW_64): Rename to ...
(MASK_VECTOR_ELEN_64): ... this.
(MASK_VECTOR_EEW_FP_32): Rename to ...
(MASK_VECTOR_ELEN_FP_32): ... this.
(MASK_VECTOR_EEW_FP_64): Rename to ...
(MASK_VECTOR_ELEN_FP_64): ... this.
(TARGET_VECTOR_ELEN_32): New.
(TARGET_VECTOR_ELEN_64): Ditto.
(TARGET_VECTOR_ELEN_FP_32): Ditto.
(TARGET_VECTOR_ELEN_FP_64): Ditto.
(TARGET_MIN_VLEN): Ditto.
* config/riscv/riscv.opt (riscv_vector_eew_flags): Rename to ...
(riscv_vector_elen_flags): ... this.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-13.c: New.
* gcc.target/riscv/arch-14.c: Ditto.
* gcc.target/riscv/arch-15.c: Ditto.
* gcc.target/riscv/predef-18.c: Ditto.
* gcc.target/riscv/predef-19.c: Ditto.
* gcc.target/riscv/predef-20.c: Ditto.
Diffstat (limited to 'gcc/common')
| -rw-r--r-- | gcc/common/config/riscv/riscv-common.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 48c4fab..1501242 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -1116,16 +1116,16 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zve64f", &gcc_options::x_target_flags, MASK_VECTOR}, {"zve64d", &gcc_options::x_target_flags, MASK_VECTOR}, - /* We don't need to put complete EEW/EEW_FP info here, due to the + /* We don't need to put complete ELEN/ELEN_FP info here, due to the implication relation of vector extension. - e.g. v -> zve64d ... zve32x, so v has set MASK_VECTOR_EEW_FP_64, - MASK_VECTOR_EEW_FP_32, MASK_VECTOR_EEW_64 and MASK_VECTOR_EEW_32 + e.g. v -> zve64d ... zve32x, so v has set MASK_VECTOR_ELEN_FP_64, + MASK_VECTOR_ELEN_FP_32, MASK_VECTOR_ELEN_64 and MASK_VECTOR_ELEN_32 due to the extension implication. */ - {"zve32x", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_32}, - {"zve32f", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32}, - {"zve64x", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_64}, - {"zve64f", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32}, - {"zve64d", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_64}, + {"zve32x", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32}, + {"zve32f", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32}, + {"zve64x", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64}, + {"zve64f", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32}, + {"zve64d", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64}, {"zvl32b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B}, {"zvl64b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B}, |