RISC-V: Support zfh and zfhmin extension

Zfh and Zfhmin are extensions for IEEE half precision, both are ratified
in Jan. 2022[1]:

- Zfh has full set of operation like F or D for single or double precision.
- Zfhmin has only provide minimal support for half precision operation,
  like conversion, load, store and move instructions.

[1] https://github.com/riscv/riscv-isa-manual/commit/b35a54079e0da11740ce5b1e6db999d1d5172768

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc (riscv_implied_info): Add
	zfh and zfhmin.
	(riscv_ext_version_table): Ditto.
	(riscv_ext_flag_table): Ditto.
	* config/riscv/riscv-opts.h (MASK_ZFHMIN): New.
	(MASK_ZFH): Ditto.
	(TARGET_ZFHMIN): Ditto.
	(TARGET_ZFH): Ditto.
	* config/riscv/riscv.cc (riscv_output_move): Handle HFmode move
	for zfh and zfhmin.
	(riscv_emit_float_compare): Handle HFmode.
	* config/riscv/riscv.md (ANYF): Add HF.
	(SOFTF): Add HF.
	(load): Ditto.
	(store): Ditto.
	(truncsfhf2): New.
	(truncdfhf2): Ditto.
	(extendhfsf2): Ditto.
	(extendhfdf2): Ditto.
	(*movhf_hardfloat): Ditto.
	(*movhf_softfloat): Make sure not ZFHMIN.
	* config/riscv/riscv.opt (riscv_zf_subext): New.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/_Float16-zfh-1.c: New.
	* gcc.target/riscv/_Float16-zfh-2.c: Ditto.
	* gcc.target/riscv/_Float16-zfh-3.c: Ditto.
	* gcc.target/riscv/_Float16-zfhmin-1.c: Ditto.
	* gcc.target/riscv/_Float16-zfhmin-2.c: Ditto.
	* gcc.target/riscv/_Float16-zfhmin-3.c: Ditto.
	* gcc.target/riscv/arch-16.c: Ditto.
	* gcc.target/riscv/arch-17.c: Ditto.
	* gcc.target/riscv/predef-21.c: Ditto.
	* gcc.target/riscv/predef-22.c: Ditto.

1 files changed, 8 insertions, 0 deletions

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 0e5be2c..4ee1b31 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -96,6 +96,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zvl32768b", "zvl16384b"},
   {"zvl65536b", "zvl32768b"},
 
+  {"zfh", "zfhmin"},
+  {"zfhmin", "f"},
+
   {NULL, NULL}
 };
 
@@ -193,6 +196,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfh",       ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zfhmin",    ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1148,6 +1154,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B},
   {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B},
 
+  {"zfhmin",    &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
+  {"zfh",       &gcc_options::x_riscv_zf_subext, MASK_ZFH},
 
   {NULL, NULL, 0}
 };