aboutsummaryrefslogtreecommitdiff
path: root/gcc/common
AgeCommit message (Expand)AuthorFilesLines
2025-11-26Revert "[PATCH v3] RISC-V: Implement RISC-V profile macro support"Jeff Law1-41/+0
2025-11-19i386: Add AVX10.1, AVX10.2, APX_F and MOVRS to Nova LakeHaochen Jiang1-1/+1
2025-11-17GCC, meet C++20Jakub Jelinek1-2/+2
2025-11-11LoongArch: Implement TARGET_GENERATE_VERSION_DISPATCHER_BODY.Lulu Cheng1-0/+41
2025-10-22Initial Nova Lake SupportHaochen Jiang3-0/+20
2025-10-15Initial Wildcat Lake SupportHaochen Jiang2-0/+4
2025-10-14i386: Remove AMX-TRANSPOSE supportHaochen Jiang4-25/+3
2025-10-13[PATCH v3] RISC-V: Implement RISC-V profile macro supportZhongyao Chen1-0/+41
2025-10-11Allow target to chose address-space for artificial rodata.Georg-Johann Lay1-6/+5
2025-10-10x86: Fixes for AMD znver5 enablementUmesh Kalvakuntla1-1/+11
2025-09-15RISC-V: Configure Profiles definitions in the definition file.Jiawei1-55/+9
2025-09-10AVR: Disable tree-switch-conversion per default.Georg-Johann Lay1-0/+7
2025-09-07RISC-V: Add support for the XAndesvpackfph ISA extension.Kuan-Lin Chen1-1/+2
2025-09-06RISC-V: Add support for the XAndesvbfhcvt ISA extension.Kuan-Lin Chen1-0/+2
2025-09-04RISC-V: Fix extension subset check in riscv_can_inline_pKito Cheng1-1/+1
2025-08-21pru: Add options to disable MUL/FILL/ZERO instructionsDimitar Dimitrov1-1/+2
2025-08-15RISC-V: Allow errors to be suppressed when parsing architecturesRichard Sandiford1-74/+95
2025-08-06RISC-V: Support -march=unsetKito Cheng1-0/+5
2025-07-31AVR: rtl-optimization/121340 - New mini-pass to undo superfluous moves from i...Georg-Johann Lay1-0/+1
2025-07-31libgcc: Update FMV features to latest ACLE spec 2024Q4Wilco Dijkstra1-12/+13
2025-07-29RISC-V: Remove use of structured binding to fix compiler warningChristoph Müllner1-1/+2
2025-07-16i386: Decouple AMX-AVX512 from AVX10.2 and imply AVX512FHaochen Jiang1-7/+6
2025-06-25x86: Update -mtune=intel for Diamond Rapids/Clearwater ForestH.J. Lu1-1/+1
2025-06-25RISC-V: Add Profiles RVA/B23S64 support.Jiawei1-1/+17
2025-06-24AArch64: propose -mmax-vectorization as an option to override vector costingTamar Christina1-0/+4
2025-06-16RISC-V: Update Profiles string in RV23.Jiawei1-3/+3
2025-06-05RISC-V: Don't use structured binding in riscv-common.ccKito Cheng1-9/+18
2025-05-23RISC-V: Support CPUs in -march.Robin Dapp1-7/+12
2025-05-19RISC-V: Fix the warning of temporary object dangling references.Dongyan Chen1-2/+2
2025-05-19i386: Remove avx10.1-256/512 and evex512 optionsHaochen Jiang4-67/+21
2025-05-14RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup issueKito Cheng1-1/+1
2025-05-13RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_info_t dataKito Cheng1-194/+27
2025-05-13RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_info_t dataKito Cheng1-250/+22
2025-05-13RISC-V: Drop riscv_implied_info and riscv_combine_info in favor of riscv_ext_...Kito Cheng1-285/+66
2025-05-13RISC-V: Introduce riscv_ext_info_t to hold extension metadataKito Cheng1-14/+177
2025-05-13RISC-V: Adjust riscv_can_inline_pKito Cheng1-17/+0
2025-05-13RISC-V: Use riscv-ext.def to generate target options and variablesKito Cheng1-51/+51
2025-05-12RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions.Dongyan Chen1-0/+36
2025-05-12RISC-V: Support for zilsd and zclsd extensions.Dongyan Chen1-0/+16
2025-05-11RISC-V: Support RISC-V Profiles 23.Jiawei1-0/+16
2025-05-11RISC-V: Support RISC-V Profiles 20/22.Jiawei1-3/+82
2025-05-07[PATCH] RISC-V: Minimal support for zama16b extension.Dongyan Chen1-0/+2
2025-05-06[PATCH] RISC-V: Minimal support for sdtrig and ssstrict extensions.Dongyan Chen1-0/+3
2025-05-06[PATCH] RISC-V: Recognized svadu and svade extensionMingzhu Yan1-3/+7
2025-04-30RISC-V: Fix missing implied Zicsr from Zve32xJerry Zhang Jian1-0/+1
2025-04-26Refactor msse4 and mno-sse4.liuhongt1-11/+12
2025-04-24[PATCH] RISC-V: Imply C from Zca whenever possible [PR119122]Yuriy Kolerov1-0/+31
2025-04-13s390: Support z17 processor nameStefan Schulze Frielinghaus1-2/+2
2025-04-01target/119549 - fixup handling of -mno-sse4 in target attributeRichard Biener1-0/+2
2025-03-24i386: Raise deprecate warning for -mavx10.1-256/512 and -mevex512 while add -...Haochen Jiang4-16/+17