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2023-08-22Support setting V-env LFSR bits with a compiler flag (#43)HEADmasterJerry Zhao1-2/+6
This makes it easier to support tests with large memory footprints, as the default 63 pages may be insufficient
2023-03-16Cope with presence of Smrnmi extensionAndrew Waterman1-0/+2
Enable RNMIs if the extension is present, as the feature affects trap behavior when RNMIs are masked.
2023-03-03Increase v env stack sizeAndrew Waterman1-1/+1
Resolves https://github.com/riscv-software-src/riscv-tests/issues/460
2023-02-02env: trap and page fault filter mechanism (#40)deepak04142-0/+25
Certain tests (particularly negative) may require a fault to occur. However in order to pass the tests, page fault and traps must return back to the tests. This patch add support for page fault and trap filtering in env. Signed-off-by: Deepak Gupta <debug@rivosinc.com>
2022-01-31Reverse memcpy direction when evicts a page. (#34)eistar1-1/+1
In "evict" function in v/vm.c, when evict a dirty page in user space, memcpy should be from that page, rather than to evicted page.
2021-07-18Fix __clear_cache(0, 0) compilation issue (#30)Daniel Lustig1-1/+1
See also https://github.com/riscv/riscv-pk/pull/240
2020-11-24v/entry.S: replace sbadaddr with stvalGokturk Yuksek1-1/+1
The RISC-V Privileged ISA v1.10 uses stval instead of sbadaddr. Although GCC can cope with sbadaddr, clang cannot. It fails with: error: operand must be a valid system register name or an integer in the range [0, 4095]
2020-11-24Replace sptbr with satp throughoutGokturk Yuksek1-3/+3
The RISC-V Privileged ISA v1.10 uses satp instead of sptbr. Although GCC can cope with sptbr, clang cannot. It fails with: error: operand must be a valid system register name or an integer in the range [0, 4095] Modified the variable name in vm.c as well to ensure consistency and avoid possible confusion.
2020-07-14fix a building errorZhi Yong Wu1-2/+2
riscv64-unknown-elf-gcc -march=rv32g -mabi=ilp32 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -DENTROPY=0xf7930f7 -std=gnu99 -O2 -I/data/riscv/riscv-tools/riscv-tests/isa/../env/v -I/data/riscv/riscv-tools/riscv-tests/isa/macros/scalar -T/data/riscv/riscv-tools/riscv-tests/isa/../env/v/link.ld /data/riscv/riscv-tools/riscv-tests/isa/../env/v/entry.S /data/riscv/riscv-tools/riscv-tests/isa/../env/v/*.c rv32ui/simple.S -o rv32ui-v-simple /opt/riscv/lib/gcc/riscv64-unknown-elf/10.1.0/../../../../riscv64-unknown-elf/bin/ld: /tmp/cc8oFAkO.o: in function `tohost': (.tohost+0x0): multiple definition of `tohost'; /tmp/ccOTKaAa.o:(.sbss+0x10): first defined here /opt/riscv/lib/gcc/riscv64-unknown-elf/10.1.0/../../../../riscv64-unknown-elf/bin/ld: /tmp/cc8oFAkO.o: in function `fromhost': (.tohost+0x40): multiple definition of `fromhost'; /tmp/ccOTKaAa.o:(.sbss+0x8): first defined here collect2: error: ld returned 1 exit status /data/riscv/riscv-tools/riscv-tests/isa/Makefile:74: recipe for target 'rv32ui-v-simple' failed make[1]: *** [rv32ui-v-simple] Error 1 make[1]: Leaving directory '/data/riscv/riscv-tools/riscv-tests/isa' Makefile:28: recipe for target 'isa' failed make: *** [isa] Error 2 Signed-off-by: Zhi Yong Wu <zhiyong.wu@sophgo.com>
2020-04-14encoding: add new VCSR for vector 0.9Chih-Min Chao1-1/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-05enable vector unit in V environment (#20)Han-Kuan Chen1-0/+3
2020-03-02restore mtvec (#19)Han-Kuan Chen1-1/+1
2020-02-27Enable vector unit in V environment by defaultAndrew Waterman1-2/+2
2019-12-16Initialize all the x-registers for determinismAndrew Waterman1-0/+32
This isn't required for correctness, but it helps debugging (and, in a few restricted scenarios, it avoids x-prop issues). Closes #16
2019-08-15Don't truncate the LFSR to 32 bitsAndrew Waterman1-2/+2
This caused it to collapse to 0, preventing coherence_torture from doing anything interesting at all...
2019-02-19Support testing Sv48 with -DSv48 optionAndrew Waterman1-21/+47
2019-01-04Align entry points for RVC compilationAndrew Waterman1-0/+4
2018-09-23Avoid writing reserved values to pmpaddr CSRAndrew Waterman1-1/+2
2018-09-06Enable EXTRA_INIT macro to work in VM environment (#10)Michael McKeown2-0/+5
2017-11-27Rename sptbr to satpAndrew Waterman1-3/+3
2017-08-16Inform GCC that "sfence.vma" clobbers memoryPalmer Dabbelt1-1/+1
2017-05-01Set ELF entry point correctlyAndrew Waterman1-2/+2
2017-03-30New PMP encodingAndrew Waterman1-1/+1
2017-03-29Test sstatus.SUM more thoroughly by keeping it usually disabledAndrew Waterman1-1/+6
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman1-5/+5
2017-03-23Align mtvec targetAndrew Waterman1-0/+1
2017-03-23Rely on assembler to provide PMP CSRsAndrew Waterman1-5/+4
2017-03-21Set up PMP if presentAndrew Waterman1-2/+12
2017-03-09WIP on priv-1.10Andrew Waterman1-25/+40
2016-12-06avoid non-standard predefined macrosAndrew Waterman3-8/+4
2016-08-26Disable interrupts during VM testsAndrew Waterman1-2/+3
The code doesn't support interrupts, and it was relying on the reset value of the mie register (which is undefined) to disable them.
2016-08-17Avoid division in VM testsAndrew Waterman2-6/+6
so we can use the same object code on processors without the M extension
2016-07-06Update to new PTE formatAndrew Waterman1-11/+9
2016-06-15Speed up VM testsAndrew Waterman3-9/+27
2016-05-25Keep tohost/fromhost at deterministic addressAndrew Waterman1-3/+0
2016-05-03Fix multicore VM testsAndrew Waterman2-2/+5
- give harts distinct stacks - correct the address range used by coherence_torture
2016-05-02Stop using mtohost/mfromhost registersAndrew Waterman2-30/+16
2016-04-30ERET -> xRET; change memory mapAndrew Waterman2-9/+12
2016-03-14Support RV32 virtual memory testspriv-1.9Andrew Waterman3-7/+117
2016-02-28WIP on priv spec v1.9Andrew Waterman2-25/+21
2015-09-20Remove Hwacha v3 supportAndrew Waterman3-178/+2
2015-07-06Coherence torture test for VM testsAndrew Waterman1-1/+24
VM tests only support one core, so have the other cores hammer on the memory system to attempt to catch simple coherence regressions.
2015-05-19Improve coverage of VM testsAndrew Waterman3-44/+89
The supervisor code now runs in supervisor mode with negative virtual addresses. This further stresses VM and tests some RV64 corner cases.
2015-05-09Update to privileged architecture version 1.7Andrew Waterman3-57/+12
2015-04-03Rename VM_SV43 to VM_SV39Andrew Waterman1-1/+1
2015-03-27New virtual memory implementation (Sv39)Andrew Waterman2-4/+4
2015-03-17Merge [shm]call into ecall, [shm]ret into eretAndrew Waterman2-2/+2
2015-03-16clean up pt and vector environmentsYunsup Lee3-6/+5
2015-03-14Check referenced/dirty bitsAndrew Waterman1-1/+7
2015-03-12Update to new privileged specAndrew Waterman3-183/+137
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