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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-12 22:29:04 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-14 00:28:13 -0700 |
| commit | 48c6d7cfcad3a20640bfe1ec2247c26003a3b6b7 (patch) | |
| tree | 5b8b5305dcbdda968c6f4bd10e3c1546a88509fd /v | |
| parent | 197385c3d5f6c1845fdc73e2290dba5f598be292 (diff) | |
| download | env-48c6d7cfcad3a20640bfe1ec2247c26003a3b6b7.zip env-48c6d7cfcad3a20640bfe1ec2247c26003a3b6b7.tar.gz env-48c6d7cfcad3a20640bfe1ec2247c26003a3b6b7.tar.bz2 | |
encoding: add new VCSR for vector 0.9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'v')
| -rw-r--r-- | v/riscv_test.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/v/riscv_test.h b/v/riscv_test.h index f9b4f66..c74e05d 100644 --- a/v/riscv_test.h +++ b/v/riscv_test.h @@ -13,7 +13,9 @@ #define RVTEST_FP_ENABLE fssr x0 #undef RVTEST_VECTOR_ENABLE -#define RVTEST_VECTOR_ENABLE fssr x0 +#define RVTEST_VECTOR_ENABLE \ + csrwi fcsr, 0; \ + csrwi vcsr, 0; #undef RVTEST_CODE_BEGIN #define RVTEST_CODE_BEGIN \ |