Update to new privileged spec

3 files changed, 137 insertions, 183 deletions

diff --git a/v/entry.S b/v/entry.S
index 96f0ca5..68c0f0a 100644
--- a/v/entry.S
+++ b/v/entry.S
@@ -13,166 +13,143 @@
 #define STACK_TOP (_end + 131072)
 
   .text
-  .global _start
-_start:
-  la sp, STACK_TOP
+  .align 6
+entry_from_user:
+  j trap_entry
+
+  .align 6
+entry_from_supervisor:
+  j double_fault
+
+  .align 6
+entry_from_hypervisor:
+  j double_fault
+
+  .align 6
+entry_from_machine:
+  j double_fault
+
+  .align 6
+power_on_reset:
+  la sp, STACK_TOP - SIZEOF_TRAPFRAME_T
+  csrw mscratch, sp
   li a1, 1337
   la a0, userstart
   j vm_boot
 
-save_tf:  # write the trap frame onto the stack
+  .globl  pop_tf
+pop_tf:
+  csrc mstatus, MSTATUS_IE
+  LOAD  t0,33*REGBYTES(a0)
+  csrw  mepc,t0
+  LOAD  x1,1*REGBYTES(a0)
+  LOAD  x2,2*REGBYTES(a0)
+  LOAD  x3,3*REGBYTES(a0)
+  LOAD  x4,4*REGBYTES(a0)
+  LOAD  x5,5*REGBYTES(a0)
+  LOAD  x6,6*REGBYTES(a0)
+  LOAD  x7,7*REGBYTES(a0)
+  LOAD  x8,8*REGBYTES(a0)
+  LOAD  x9,9*REGBYTES(a0)
+  LOAD  x11,11*REGBYTES(a0)
+  LOAD  x12,12*REGBYTES(a0)
+  LOAD  x13,13*REGBYTES(a0)
+  LOAD  x14,14*REGBYTES(a0)
+  LOAD  x15,15*REGBYTES(a0)
+  LOAD  x16,16*REGBYTES(a0)
+  LOAD  x17,17*REGBYTES(a0)
+  LOAD  x18,18*REGBYTES(a0)
+  LOAD  x19,19*REGBYTES(a0)
+  LOAD  x20,20*REGBYTES(a0)
+  LOAD  x21,21*REGBYTES(a0)
+  LOAD  x22,22*REGBYTES(a0)
+  LOAD  x23,23*REGBYTES(a0)
+  LOAD  x24,24*REGBYTES(a0)
+  LOAD  x25,25*REGBYTES(a0)
+  LOAD  x26,26*REGBYTES(a0)
+  LOAD  x27,27*REGBYTES(a0)
+  LOAD  x28,28*REGBYTES(a0)
+  LOAD  x29,29*REGBYTES(a0)
+  LOAD  x30,30*REGBYTES(a0)
+  LOAD  x31,31*REGBYTES(a0)
+  LOAD  a0,10*REGBYTES(a0)
+  mret
+
+  .global  trap_entry
+trap_entry:
+  csrrw sp, mscratch, sp
 
   # save gprs
-  STORE  x3,3*REGBYTES(x2)
-  STORE  x4,4*REGBYTES(x2)
-  STORE  x5,5*REGBYTES(x2)
-  STORE  x6,6*REGBYTES(x2)
-  STORE  x7,7*REGBYTES(x2)
-  STORE  x8,8*REGBYTES(x2)
-  STORE  x9,9*REGBYTES(x2)
-  STORE  x10,10*REGBYTES(x2)
-  STORE  x11,11*REGBYTES(x2)
-  STORE  x12,12*REGBYTES(x2)
-  STORE  x13,13*REGBYTES(x2)
-  STORE  x14,14*REGBYTES(x2)
-  STORE  x15,15*REGBYTES(x2)
-  STORE  x16,16*REGBYTES(x2)
-  STORE  x17,17*REGBYTES(x2)
-  STORE  x18,18*REGBYTES(x2)
-  STORE  x19,19*REGBYTES(x2)
-  STORE  x20,20*REGBYTES(x2)
-  STORE  x21,21*REGBYTES(x2)
-  STORE  x22,22*REGBYTES(x2)
-  STORE  x23,23*REGBYTES(x2)
-  STORE  x24,24*REGBYTES(x2)
-  STORE  x25,25*REGBYTES(x2)
-  STORE  x26,26*REGBYTES(x2)
-  STORE  x27,27*REGBYTES(x2)
-  STORE  x28,28*REGBYTES(x2)
-  STORE  x29,29*REGBYTES(x2)
-  STORE  x30,30*REGBYTES(x2)
-  STORE  x31,31*REGBYTES(x2)
-
-  csrr   x3,sup0
-  STORE  x3,1*REGBYTES(x2)          # x1 is in sup0
-  csrr   x3,sup1
-  STORE  x3,2*REGBYTES(x2)          # x2 is in sup1
+  STORE  x1,1*REGBYTES(sp)
+  STORE  x3,3*REGBYTES(sp)
+  STORE  x4,4*REGBYTES(sp)
+  STORE  x5,5*REGBYTES(sp)
+  STORE  x6,6*REGBYTES(sp)
+  STORE  x7,7*REGBYTES(sp)
+  STORE  x8,8*REGBYTES(sp)
+  STORE  x9,9*REGBYTES(sp)
+  STORE  x10,10*REGBYTES(sp)
+  STORE  x11,11*REGBYTES(sp)
+  STORE  x12,12*REGBYTES(sp)
+  STORE  x13,13*REGBYTES(sp)
+  STORE  x14,14*REGBYTES(sp)
+  STORE  x15,15*REGBYTES(sp)
+  STORE  x16,16*REGBYTES(sp)
+  STORE  x17,17*REGBYTES(sp)
+  STORE  x18,18*REGBYTES(sp)
+  STORE  x19,19*REGBYTES(sp)
+  STORE  x20,20*REGBYTES(sp)
+  STORE  x21,21*REGBYTES(sp)
+  STORE  x22,22*REGBYTES(sp)
+  STORE  x23,23*REGBYTES(sp)
+  STORE  x24,24*REGBYTES(sp)
+  STORE  x25,25*REGBYTES(sp)
+  STORE  x26,26*REGBYTES(sp)
+  STORE  x27,27*REGBYTES(sp)
+  STORE  x28,28*REGBYTES(sp)
+  STORE  x29,29*REGBYTES(sp)
+  STORE  x30,30*REGBYTES(sp)
+  STORE  x31,31*REGBYTES(sp)
+
+  csrrw  t0,mscratch,sp
+  STORE  t0,2*REGBYTES(sp)
 
   # get sr, epc, badvaddr, cause
-  csrr   x3,status          # sr
-  STORE  x3,32*REGBYTES(x2)
-  csrr   x4,epc          # epc
-  STORE  x4,33*REGBYTES(x2)
-  csrr   x3,badvaddr      # badvaddr
-  STORE  x3,34*REGBYTES(x2)
-  csrr   x3,cause        # cause
-  STORE  x3,35*REGBYTES(x2)
+  csrr   t0,mstatus
+  STORE  t0,32*REGBYTES(sp)
+  csrr   t0,mepc
+  STORE  t0,33*REGBYTES(sp)
+  csrr   t0,mbadaddr
+  STORE  t0,34*REGBYTES(sp)
+  csrr   t0,mcause
+  STORE  t0,35*REGBYTES(sp)
 
   # get hwacha cause if IRQ_COP
   # vxcptcause clears hwacha interrupt bit
 
-  bge   x3,x0,1f
-  slli  x3,x3,1 # clearing MSB of cause
-  srli  x3,x3,1 # clearing MSB of cause
-  li    x4,IRQ_COP
-  bne   x3,x4,1f
-  vxcptcause x3
-  STORE  x3,36*REGBYTES(x2)
+  bgez  t0,1f
+  slli  t0,t0,1 # clearing MSB of cause
+  srli  t0,t0,1 # clearing MSB of cause
+  li    t1,IRQ_COP
+  bne   t0,t1,1f
+  vxcptcause t0
+  STORE  t0,36*REGBYTES(sp)
 1:
 
-  jr x1
-
-  .globl  pop_tf
-pop_tf:  # write the trap frame onto the stack
-  # restore gprs
-  LOAD  a1,32*REGBYTES(a0)  # restore sr (should disable interrupts)
-  csrw  status,a1
-
-  LOAD  x1,1*REGBYTES(a0)
-  LOAD  x2,2*REGBYTES(a0)
-  csrw  sup0,x1
-  csrw  sup1,x2
-  move  x1,a0
-  LOAD  x3,3*REGBYTES(x1)
-  LOAD  x4,4*REGBYTES(x1)
-  LOAD  x5,5*REGBYTES(x1)
-  LOAD  x6,6*REGBYTES(x1)
-  LOAD  x7,7*REGBYTES(x1)
-  LOAD  x8,8*REGBYTES(x1)
-  LOAD  x9,9*REGBYTES(x1)
-  LOAD  x10,10*REGBYTES(x1)
-  LOAD  x11,11*REGBYTES(x1)
-  LOAD  x12,12*REGBYTES(x1)
-  LOAD  x13,13*REGBYTES(x1)
-  LOAD  x14,14*REGBYTES(x1)
-  LOAD  x15,15*REGBYTES(x1)
-  LOAD  x16,16*REGBYTES(x1)
-  LOAD  x17,17*REGBYTES(x1)
-  LOAD  x18,18*REGBYTES(x1)
-  LOAD  x19,19*REGBYTES(x1)
-  LOAD  x20,20*REGBYTES(x1)
-  LOAD  x21,21*REGBYTES(x1)
-  LOAD  x22,22*REGBYTES(x1)
-  LOAD  x23,23*REGBYTES(x1)
-  LOAD  x24,24*REGBYTES(x1)
-  LOAD  x25,25*REGBYTES(x1)
-  LOAD  x26,26*REGBYTES(x1)
-  LOAD  x27,27*REGBYTES(x1)
-  LOAD  x28,28*REGBYTES(x1)
-  LOAD  x29,29*REGBYTES(x1)
-  LOAD  x30,30*REGBYTES(x1)
-  LOAD  x31,31*REGBYTES(x1)
-
-  # gtfo!
-  LOAD  x2,33*REGBYTES(x1)
-  csrw  epc,x2
-  csrr  x1,sup0
-  csrr  x2,sup1
-  sret
-
-  .global  trap_entry
-trap_entry:
-  csrw sup0,x1
-  csrw sup1,x2
-
-  # coming from kernel?
-  csrr  x1,status
-  and   x1,x1,SR_PS
-  bnez  x1, 1f
-
-  # no, so start at the top of the stack
-  la    x2,STACK_TOP-SIZEOF_TRAPFRAME_T
-  jal   x1, save_tf
-  move  sp,x2
-  csrs  status,SR_EI
   move  a0,sp
-  csrr  t0,status
-  and   t0,t0,SR_EA
+  csrr  t0,mstatus
+  li    t1, MSTATUS_XS
+  and   t0,t0,t1
   beqz  t0,2f
+
+  # disable saving vector state for now
   addi  t0,sp,SIZEOF_TRAPFRAME_T_SCALAR
 
   # rocket currently doesn't support vxcptsave/vxcptrestore natively
-  csrr  x3,impl 
-  li    x4,IMPL_ROCKET
-  bne   x3,x4,3f
   vgetcfg x4
   STORE x4,0*REGBYTES(t0)
   vgetvl x4
   STORE x4,1*REGBYTES(t0)
   addi  t0,t0,2*REGBYTES
   vxcptevac t0
-  j     2f
-
-  # native vxcptsave
-3:vxcptsave t0
-2:jal   handle_trap
-
-  # when coming from kernel, continue below its stack
-  # we assume vector unit wasn't used in kernel
-1:addi  x2,sp,-SIZEOF_TRAPFRAME_T_SCALAR
-  jal   x1, save_tf
-  move  sp,x2
-  csrs  status,SR_EI
-  move  a0,sp
-  jal   handle_trap
-  unimp
+2:j handle_trap
diff --git a/v/link.ld b/v/link.ld
index 4efeaaa..3ae9717 100644
--- a/v/link.ld
+++ b/v/link.ld
@@ -13,11 +13,6 @@
 
 OUTPUT_ARCH( "riscv" )
 
-/* The ENTRY command specifies the entry point (ie. first instruction
-   to execute). The symbol _start should be defined in each test. */
-
-ENTRY( _start )
-
 /*----------------------------------------------------------------------*/
 /* Sections                                                             */
 /*----------------------------------------------------------------------*/
@@ -26,7 +21,7 @@ SECTIONS
 {
 
   /* text: test code section */
-  . = 0x00002000;
+  . = 0;
   .text :
   {
     *(.text)
diff --git a/v/vm.c b/v/vm.c
index a57a136..10fc0cd 100644
--- a/v/vm.c
+++ b/v/vm.c
@@ -12,13 +12,13 @@ void pop_tf(trapframe_t*);
 static void cputchar(int x)
 {
   while (swap_csr(tohost, 0x0101000000000000 | (unsigned char)x));
+  while (swap_csr(fromhost, 0) == 0);
 }
 
 static void cputstring(const char* s)
 {
   while(*s)
     cputchar(*s++);
-  cputchar('\n');
 }
 
 static void terminate(int code)
@@ -31,12 +31,10 @@ static void terminate(int code)
 #define stringify(x) stringify1(x)
 #define assert(x) do { \
   if (x) break; \
-  cputstring("Assertion failed: " stringify(x)); \
+  cputstring("Assertion failed: " stringify(x) "\n"); \
   terminate(3); \
 } while(0)
 
-#define RELOC(x) ((typeof(x))((char*)(x) + (PGSIZE*MAX_TEST_PAGES)))
-
 typedef struct { pte_t addr; void* next; } freelist_t;
 
 pte_t l1pt[PTES_PER_PT] __attribute__((aligned(PGSIZE)));
@@ -61,13 +59,13 @@ void printhex(uint64_t x)
 
 void evict(unsigned long addr)
 {
-  assert(addr >= PGSIZE && addr < RELOC(0L));
+  assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
   addr = addr/PGSIZE*PGSIZE;
 
   freelist_t* node = &user_mapping[addr/PGSIZE];
   if (node->addr)
   {
-    memcpy((void*)RELOC(addr), (void*)addr, PGSIZE);
+    memcpy((void*)addr, (void*)node->addr, PGSIZE);
     user_mapping[addr/PGSIZE].addr = 0;
 
     if (freelist_tail == 0)
@@ -82,7 +80,7 @@ void evict(unsigned long addr)
 
 void handle_fault(unsigned long addr)
 {
-  assert(addr >= PGSIZE && addr < RELOC(0L));
+  assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
   addr = addr/PGSIZE*PGSIZE;
 
   freelist_t* node = freelist_head;
@@ -92,11 +90,11 @@ void handle_fault(unsigned long addr)
     freelist_tail = 0;
 
   l3pt[addr/PGSIZE] = node->addr | PTE_UW | PTE_UR | PTE_UX | PTE_SW | PTE_SR | PTE_SX | PTE_V;
-  write_csr(fatc, 0);
+  asm volatile ("sfence.vm");
 
   assert(user_mapping[addr/PGSIZE].addr == 0);
   user_mapping[addr/PGSIZE] = *node;
-  memcpy((void*)addr, (void*)RELOC(addr), PGSIZE);
+  memcpy((void*)node->addr, (void*)addr, PGSIZE);
 
   __builtin___clear_cache(0,0);
 }
@@ -151,15 +149,12 @@ static void do_vxcptrestore(long* where)
 
 static void restore_vector(trapframe_t* tf)
 {
-  if (read_csr(impl) == IMPL_ROCKET)
-    do_vxcptrestore(tf->hwacha_opaque);
-  else
-    vxcptrestore(tf->hwacha_opaque);
+  do_vxcptrestore(tf->hwacha_opaque);
 }
 
 void handle_trap(trapframe_t* tf)
 {
-  if (tf->cause == CAUSE_SYSCALL)
+  if (tf->cause == CAUSE_SCALL)
   {
     int n = tf->gpr[10];
 
@@ -201,10 +196,8 @@ void handle_trap(trapframe_t* tf)
     assert(!"unexpected exception");
 
 out:
-  if (!(tf->sr & SR_PS) && (tf->sr & SR_EA)) {
+  if (!(tf->sr & MSTATUS_PRV1) && (tf->sr & MSTATUS_XS))
     restore_vector(tf);
-    tf->sr |= SR_PEI;
-  }
   pop_tf(tf);
 }
 
@@ -214,34 +207,20 @@ void vm_boot(long test_addr, long seed)
 
   assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t));
 
-  assert(MAX_TEST_PAGES*2 < PTES_PER_PT);
   l1pt[0] = (pte_t)l2pt | PTE_V | PTE_T;
   l2pt[0] = (pte_t)l3pt | PTE_V | PTE_T;
-  for (long i = 0; i < MAX_TEST_PAGES; i++)
-    l3pt[i] = l3pt[i+MAX_TEST_PAGES] = (i*PGSIZE) | PTE_SW | PTE_SR | PTE_SX | PTE_V;
-
-  write_csr(ptbr, l1pt);
-  write_csr(status, read_csr(status) | SR_VM | SR_EF);
-
-  // relocate
-  long adjustment = RELOC(0L), tmp;
-  write_csr(evec, (char*)&trap_entry + adjustment);
-  asm volatile ("add sp, sp, %1\n"
-                "jal %0, 1f\n"
-                "1: add %0, %0, %1\n"
-                "jr %0, 8"
-                : "=&r"(tmp)
-                : "r"(adjustment));
-
-  memset(l3pt, 0, MAX_TEST_PAGES*sizeof(pte_t));
-  write_csr(fatc, 0);
+  write_csr(sptbr, l1pt);
+  set_csr(mstatus, MSTATUS_IE1 | MSTATUS_FS /* | MSTATUS_XS */ | MSTATUS_MPRV);
+  clear_csr(mstatus, MSTATUS_VM | MSTATUS_UA | MSTATUS_PRV1);
+  set_csr(mstatus, (long)VM_SV43 << __builtin_ctzl(MSTATUS_VM));
+  set_csr(mstatus, (long)UA_RV64 << __builtin_ctzl(MSTATUS_UA));
 
   seed = 1 + (seed % MAX_TEST_PAGES);
   freelist_head = &freelist_nodes[0];
   freelist_tail = &freelist_nodes[MAX_TEST_PAGES-1];
   for (long i = 0; i < MAX_TEST_PAGES; i++)
   {
-    freelist_nodes[i].addr = (MAX_TEST_PAGES+i)*PGSIZE;
+    freelist_nodes[i].addr = (MAX_TEST_PAGES + seed)*PGSIZE;
     freelist_nodes[i].next = &freelist_nodes[i+1];
     seed = LFSR_NEXT(seed);
   }
@@ -249,8 +228,11 @@ void vm_boot(long test_addr, long seed)
 
   trapframe_t tf;
   memset(&tf, 0, sizeof(tf));
-  tf.sr = SR_PEI | ((1 << IRQ_COP) << SR_IM_SHIFT) | SR_EF | SR_EA | SR_S | SR_U64 | SR_S64 | SR_VM;
   tf.epc = test_addr;
-
   pop_tf(&tf);
 }
+
+void double_fault()
+{
+  assert(!"double fault!");
+}