diff options
author | Andrew Waterman <andrew@sifive.com> | 2017-03-21 15:50:13 -0700 |
---|---|---|
committer | Andrew Waterman <andrew@sifive.com> | 2017-03-21 15:50:13 -0700 |
commit | 9e43ec4eafc7a96b9aa19397ffbc9dbeb161efb2 (patch) | |
tree | 67856a03ebd1e8177b0de7b36d8d2ea0dcec9fb0 /v | |
parent | 497efbd0fa104b70f058ea550ed0c7f8a554662b (diff) | |
download | env-9e43ec4eafc7a96b9aa19397ffbc9dbeb161efb2.zip env-9e43ec4eafc7a96b9aa19397ffbc9dbeb161efb2.tar.gz env-9e43ec4eafc7a96b9aa19397ffbc9dbeb161efb2.tar.bz2 |
Set up PMP if present
Diffstat (limited to 'v')
-rw-r--r-- | v/vm.c | 14 |
1 files changed, 12 insertions, 2 deletions
@@ -228,6 +228,16 @@ void vm_boot(uintptr_t test_addr) write_csr(sptbr, ((uintptr_t)l1pt >> PGSHIFT) | (vm_choice * (SPTBR_MODE & ~(SPTBR_MODE<<1)))); + // Set up PMPs if present, ignoring illegal instruction trap if not. + uintptr_t pmpc = PMP_EN | PMP_NAPOT | PMP_M | PMP_R | PMP_W | PMP_X; + asm volatile ("la t0, 1f\n\t" + "csrw mtvec, t0\n\t" + "csrw %2, %3\n\t" + "csrw %0, %1\n\t" + "1:" + :: "i" (CSR_PMPCFG0), "r" (pmpc), "i" (CSR_PMPADDR0), "r" (-1) + : "t0"); + // set up supervisor trap handling write_csr(stvec, pa2kva(trap_entry)); write_csr(sscratch, pa2kva(read_csr(mscratch))); @@ -236,8 +246,8 @@ void vm_boot(uintptr_t test_addr) (1 << CAUSE_FAULT_FETCH) | (1 << CAUSE_FAULT_LOAD) | (1 << CAUSE_FAULT_STORE)); - // FPU on; accelerator on - write_csr(mstatus, MSTATUS_FS | MSTATUS_XS); + // FPU on; accelerator on; allow supervisor access to user memory access + write_csr(mstatus, MSTATUS_FS | MSTATUS_XS | MSTATUS_SUM); write_csr(mie, 0); random = 1 + (random % MAX_TEST_PAGES); |