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author | Andrew Waterman <andrew@sifive.com> | 2018-09-23 21:11:53 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2018-09-23 21:12:06 -0700 |
commit | 4c356d46aace73c1562816a41e0f63948bdb0497 (patch) | |
tree | 0dffa5b7d95a660f84773f7d6414ece04b4bd0e4 /v | |
parent | 8d6a8bac53b6aeedc3e460a4b9cdcb070591f697 (diff) | |
download | env-4c356d46aace73c1562816a41e0f63948bdb0497.zip env-4c356d46aace73c1562816a41e0f63948bdb0497.tar.gz env-4c356d46aace73c1562816a41e0f63948bdb0497.tar.bz2 |
Avoid writing reserved values to pmpaddr CSR
Diffstat (limited to 'v')
-rw-r--r-- | v/vm.c | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -235,13 +235,14 @@ void vm_boot(uintptr_t test_addr) // Set up PMPs if present, ignoring illegal instruction trap if not. uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X; + uintptr_t pmpa = ((uintptr_t)1 << (__riscv_xlen == 32 ? 31 : 53)) - 1; asm volatile ("la t0, 1f\n\t" "csrrw t0, mtvec, t0\n\t" "csrw pmpaddr0, %1\n\t" "csrw pmpcfg0, %0\n\t" ".align 2\n\t" "1:" - : : "r" (pmpc), "r" (-1UL) : "t0"); + : : "r" (pmpc), "r" (pmpa) : "t0"); // set up supervisor trap handling write_csr(stvec, pa2kva(trap_entry)); |