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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-05-03 11:13:36 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-05-03 11:13:36 -0700 |
commit | e0010519c57a2b88d0d03d38c21ba0a68f81f2e2 (patch) | |
tree | ac0b9a0365bba1b83e784489a3a6b896a8b39de6 /v | |
parent | b54a6f8e11f43ac6df310016723ef6eb2f7d3a33 (diff) | |
download | env-e0010519c57a2b88d0d03d38c21ba0a68f81f2e2.zip env-e0010519c57a2b88d0d03d38c21ba0a68f81f2e2.tar.gz env-e0010519c57a2b88d0d03d38c21ba0a68f81f2e2.tar.bz2 |
Fix multicore VM tests
- give harts distinct stacks
- correct the address range used by coherence_torture
Diffstat (limited to 'v')
-rw-r--r-- | v/entry.S | 5 | ||||
-rw-r--r-- | v/vm.c | 2 |
2 files changed, 5 insertions, 2 deletions
@@ -10,7 +10,7 @@ # define REGBYTES 4 #endif -#define STACK_TOP (_end + 131072) +#define STACK_TOP (_end + 4096) .section ".text.init","ax",@progbits @@ -28,6 +28,9 @@ handle_reset: la t0, trap_vector csrw mtvec, t0 la sp, STACK_TOP - SIZEOF_TRAPFRAME_T + csrr t0, mhartid + slli t0, t0, 12 + add sp, sp, t0 csrw mscratch, sp li a1, 1337 la a0, userstart @@ -175,7 +175,7 @@ static void coherence_torture() // cause coherence misses without affecting program semantics uint64_t random = ENTROPY; while (1) { - uintptr_t paddr = (random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4; + uintptr_t paddr = DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4); #ifdef __riscv_atomic if (random & 1) // perform a no-op write asm volatile ("amoadd.w zero, zero, (%0)" :: "r"(paddr)); |