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Files
Lines
2022-06-09
Test misaligned stores. (#397)
Tim Newsome
8
-0
/
+158
2022-06-07
Test misaligned loads.
Tim Newsome
8
-0
/
+160
2022-06-07
Set TESTNUM before executing code.
Tim Newsome
3
-6
/
+4
2022-06-06
Revert unaligned tests.
Tim Newsome
3
-51
/
+1
2022-06-06
Test unaligned ld accesses.
Tim Newsome
1
-0
/
+27
2022-06-06
Add unaligned test cases for lw
Tim Newsome
1
-0
/
+23
2022-06-06
Set TESTNUM before executing code.
Tim Newsome
1
-1
/
+1
2022-05-28
Permit mtval to be zero in misaligned address test, fixes #389 (#390)
Luke Wren
1
-0
/
+2
2022-03-08
Add Zfh and Svnapot to Spike ISA string
Andrew Waterman
1
-2
/
+2
2021-07-22
Fix #352 (#353)
Daniel Lustig
1
-2
/
+2
2021-07-21
Move the Svnapot test to its own folder (#351)
Daniel Lustig
4
-1
/
+10
2021-07-19
Add a test for Svnapot (#349)
Daniel Lustig
2
-0
/
+173
2021-06-01
Enable access to cycle counter before trying to write it
Andrew Waterman
1
-0
/
+13
2021-06-01
Test all four ways of reading a read-only CSR
Andrew Waterman
1
-0
/
+8
2021-05-12
Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: (#...
SLAMET RIANTO
2
-0
/
+2
2021-05-10
Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support C...
SLAMET RIANTO
3
-0
/
+52
2021-02-01
Align mtvec in rv32mi-p-shamt test
Andrew Waterman
1
-0
/
+1
2021-01-08
Don't rely on the implementation-specific WFI time limit (#318)
Paul Donahue
1
-18
/
+0
2021-01-04
Disable rv32ua/rv64ua LR/SC test case 4 (#316)
Ben Marshall
1
-8
/
+14
2020-12-16
Refactor rv64ud structural test to match format of other tests (#311)
Kathlene Hurt
1
-11
/
+13
2020-12-08
Add rd=x0 test case to csr test (#308)
Takahiro
1
-0
/
+1
2020-12-07
Fix minor typo (#307)
Takahiro
1
-1
/
+1
2020-11-20
Only attempt to build tests supported by compiler
Andrew Waterman
19
-38
/
+6
2020-11-11
add zfh (float16) test case and related macros (#301)
Chih-Min Chao
26
-0
/
+769
2020-10-19
use registers present on rv32e (#299)
Sandeep Rajendran
1
-4
/
+4
2020-03-21
Fix regression introduced by 24d7d6b68c5581c36cbdef354b1882a7a8dd52c5
Andrew Waterman
1
-7
/
+7
2020-03-21
Move self-modifying 'fence.i' ops to .data memory section (#269)
WRansohoff
1
-6
/
+14
2020-03-19
Fix comments error in fmin.S (#267)
Mohanson
2
-4
/
+4
2020-03-18
Have both rs=rd and rs!=rd cases in csr.S (#263)
Takahiro
1
-12
/
+15
2020-03-18
Fix shamt.S header (#264)
Takahiro
1
-2
/
+2
2020-03-16
Add a test case rs = rd to jalr.S (#258)
Takahiro
1
-0
/
+16
2020-03-11
Add comment explaining convoluted rv64mi-p-scall behavior
Andrew Waterman
1
-0
/
+6
2020-03-11
Revert "scall: make the intention of the test in machine mode more clear (#246)"
Andrew Waterman
1
-6
/
+1
2020-03-11
Setup a multilevel page table to avoid misaligned superpages caused by variab...
Cedric Orban
1
-0
/
+4
2020-03-06
Don't assume reset state of mscratch (#254)
Paul Donahue
1
-1
/
+1
2020-03-02
enable rv32e compatability by replacing reg x29 with reg x7 (#250)
Cedric Orban
1
-12
/
+12
2020-02-21
scall: make the intention of the test in machine mode more clear (#246)
Nils Asmussen
1
-1
/
+6
2020-02-20
Fix rv64mi-p-csr on systems with FPUs
Andrew Waterman
1
-2
/
+3
2020-01-31
Added CSR test cases on whether writing 0 to CSR works, as that might get ove...
Torbjørn Viem Ness
1
-0
/
+2
2019-11-04
Remove cruft from icache-alias test
Andrew Waterman
1
-35
/
+0
2019-11-04
Add rv64si-p-icache-alias
Andrew Waterman
2
-0
/
+177
2019-07-29
Support RV32E. Fixed #198 (#200)
Leway Colin
3
-42
/
+42
2019-04-20
masking no longer required.
Neel
1
-16
/
+0
2019-04-20
removing check for reset value of type in mcontrol
Neel
1
-10
/
+8
2019-04-20
fix for #159 #158
Neel
1
-4
/
+7
2019-03-17
Rename TEST_SRL to TEST_SRLI to avoid conflicts with another TEST_SRL (#183)
Pavel I. Kryukov
1
-18
/
+18
2019-01-26
Fix comments for shift amount. (#177)
takeoverjp
3
-3
/
+3
2018-12-18
Avoid using t3 and t4 for supporting RV32E (#173)
zhonghochen
1
-5
/
+6
2018-11-16
Test memory content on failing SC (#171)
Florian Zaruba
1
-4
/
+10
2018-09-08
RV64 s{ll,ra,rl}w tests with non-canonical values
Tommy Thorn
6
-0
/
+42
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