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2024-08-14Fit riscv-tests to newest riscv spec: renaming sptbr,sbadaddr,mbadaddr (#578)HUJIYONG2-7/+7
issue#577 In the newest riscv spec(2021 or later), two csr register "sptbr"(0x180) "s/mbadaddr"(0x243) were removed, and upgraded to "satp" "s/mtval". Together with more functions. This commit rename them to pass compile.
2024-03-19ma_addr: permit access faults in lieu of misaligned exceptionsAndrew Waterman1-1/+6
2024-02-18Fix breakpoint testAndrew Waterman1-0/+3
See https://github.com/riscv/riscv-debug-spec/blob/f510a7dd33317d0eee0f26b4fa082cd43a5ac7ea/Sdtrig.tex#L213-L214
2023-03-16Fix breakpoint.S failing when tcontrol is implemented (#463)Luke Wren1-0/+10
2022-12-07zicntr: separate cycle/instret accessibility test (#439)Chih-Min Chao2-6/+58
It is allowed that M-mode only implementation could skip cycle/instret if the Zicntr is not included. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2022-06-09Test misaligned stores. (#397)Tim Newsome4-0/+125
Assume that misaligned loads work correctly. Passes `make -C isa run` against spike (both with and without misaligned support).
2022-06-07Test misaligned loads.Tim Newsome4-0/+126
Cover lh, lw, and ld (only on rv64).
2022-05-28Permit mtval to be zero in misaligned address test, fixes #389 (#390)Luke Wren1-0/+2
2021-05-10Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support ↵SLAMET RIANTO1-0/+38
CLIC mode. (#336) illegal.S: - After the test enters supervisor mode, check if paging is supported. - If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following: -- SFENCE.VMA causing illegal instruction trap regardless of TVM. -- Access to SATP does not trap. -- Jump to the same TSR check as regular S-mode -- End test sbreak.S & scall.S: - Before checking for scause, check if the core is in CLIC-mode (mtvec[1]). - If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value. - Otherwise, don't mask off any scause bits as in the original test. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com>
2021-01-08Don't rely on the implementation-specific WFI time limit (#318)Paul Donahue1-18/+0
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset * Remove testcase that relies on the implementation-specific WFI time limit being 0.
2020-12-07Fix minor typo (#307)Takahiro1-1/+1
2020-11-20Only attempt to build tests supported by compilerAndrew Waterman1-2/+0
Resolves #303
2019-07-29Support RV32E. Fixed #198 (#200)Leway Colin1-5/+5
2019-04-20masking no longer required.Neel1-16/+0
2019-04-20removing check for reset value of type in mcontrolNeel1-10/+8
2019-04-20fix for #159 #158Neel1-4/+7
2018-12-18Avoid using t3 and t4 for supporting RV32E (#173)zhonghochen1-5/+6
2018-09-06Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) ↵Andrew Waterman1-1/+1
(#159)" This reverts commit 901a2694d5384e4ef9af8e4fb0c9a07eb24d0028, under the advisement of @tommythorn in #158.
2018-09-06breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)Tommy Thorn1-1/+1
2018-01-02Test access exception behavior for illegal addresses (#111)Andrew Waterman2-0/+71
OK'd by @palmer-dabbelt
2017-11-20Check mtval in rv64mi-p-illegal (#104)Andrew Waterman1-0/+11
Closes #103
2017-11-11Make sure that code is 4-byte aligned before disabling rvc (#100)Andrew Waterman1-0/+1
2017-10-30Declare trap handlers as global symbols. (#87)Richard Xia3-0/+4
This allows them to be referenced by other files, such as a test environment that lives in a separate compilation unit.
2017-04-14Fix illegal-instruction test when S-mode is not implementedAndrew Waterman1-10/+14
2017-04-07Retrofit rv64mi-p-illegal to test vectored interruptsAndrew Waterman1-7/+41
2017-04-07Remove defunct IPI testsAndrew Waterman2-52/+0
2017-04-05Make ma_addr test work for systems with misaligned ld/stAndrew Waterman1-34/+66
2017-03-13Test mstatus.TW, mstatus.TVM, and mstatus.TSR featuresAndrew Waterman1-1/+105
2017-03-09Check mbadaddr in ma_addr testAndrew Waterman1-0/+4
2016-12-06avoid non-standard predefined macrosAndrew Waterman3-5/+5
2016-08-26Update to new breakpoint & counter specAndrew Waterman1-26/+25
2016-07-29Add an RVC testAndrew Waterman2-3/+7
2016-07-22Move dirty bit test to rv64si directoryAndrew Waterman2-94/+0
Not sure this is quite right, since the test technically runs in M-mode. Also, remove unused rdnpc/example tests.
2016-07-11Remove instruction width assumptions to support RVCAndrew Waterman2-0/+2
2016-07-06Update to new PTE formatAndrew Waterman1-4/+4
2016-06-17Fix breakpoint test when only one breakpoint presentAndrew Waterman1-1/+8
2016-06-10Test more than one breakpoint at a time, if presentAndrew Waterman1-44/+68
2016-06-09Update breakpoint specAndrew Waterman1-4/+19
2016-06-08Don't arm breakpoint before setting break addressAndrew Waterman1-12/+11
2016-06-08Add HW breakpoint testAndrew Waterman2-0/+98
2016-05-02Remove incorrect M-mode WFI testAndrew Waterman2-9/+0
MSIP isn't supposed to be writable locally!
2016-05-02Stop using tohost/fromhost registersAndrew Waterman2-2/+15
2016-04-30ERET -> xRET; new memory mapAndrew Waterman6-1118/+17
For now, we no longer build hex files, because the programs don't start at address 0. This decision will likely be revisited.
2016-04-06Fix expected misa register value for RV32Andrew Waterman1-1/+1
2016-03-10Add missing rv32mi/rv32si testsAndrew Waterman2-3/+7
2016-03-03Some S-mode tests really only belong in M-modeAndrew Waterman2-8/+116
2016-03-03WIP on priv spec v1.9Andrew Waterman4-7/+11
2016-01-12Write 1, not 0, to MIPIAndrew Waterman1-1/+1
2015-11-16Update IPI test to work with new mechanismAndrew Waterman1-17/+3
2015-10-19Avoid REMU in timer testAndrew Waterman1-2/+7
generated by cgit v1.1 at 2024-09-17 13:45:44 +0000