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| author | Andrew Waterman <andrew@sifive.com> | 2018-09-06 18:45:14 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-09-06 18:45:14 -0700 |
| commit | 9d3bc86d85d935f498065d54ead7e568f03b2824 (patch) | |
| tree | f4baafc7eaac8a1b24514dd0c2b2de44c26b6b4d /isa/rv64mi | |
| parent | 901a2694d5384e4ef9af8e4fb0c9a07eb24d0028 (diff) | |
| download | riscv-tests-9d3bc86d85d935f498065d54ead7e568f03b2824.zip riscv-tests-9d3bc86d85d935f498065d54ead7e568f03b2824.tar.gz riscv-tests-9d3bc86d85d935f498065d54ead7e568f03b2824.tar.bz2 | |
Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)"
This reverts commit 901a2694d5384e4ef9af8e4fb0c9a07eb24d0028,
under the advisement of @tommythorn in #158.
Diffstat (limited to 'isa/rv64mi')
| -rw-r--r-- | isa/rv64mi/breakpoint.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index df415a1..647430b 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN la a2, 1f csrw tdata2, a2 - li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_EXECUTE + li a0, MCONTROL_M | MCONTROL_EXECUTE csrw tdata1, a0 # Skip if breakpoint type is unsupported. csrr a1, tdata1 |