aboutsummaryrefslogtreecommitdiff
path: root/isa/rv64mi
diff options
context:
space:
mode:
authorAndrew Waterman <waterman@cs.berkeley.edu>2016-03-02 22:33:37 -0800
committerAndrew Waterman <waterman@cs.berkeley.edu>2016-03-03 11:03:59 -0800
commit4d1491df727e9aeb5fdfeac25c22eaf24cafb908 (patch)
tree3b3639675a9eb006a0eb7cb35d89a6ba34006cea /isa/rv64mi
parenta0a3ae4841308010c6437e0f47467af97a140cda (diff)
downloadriscv-tests-4d1491df727e9aeb5fdfeac25c22eaf24cafb908.zip
riscv-tests-4d1491df727e9aeb5fdfeac25c22eaf24cafb908.tar.gz
riscv-tests-4d1491df727e9aeb5fdfeac25c22eaf24cafb908.tar.bz2
Some S-mode tests really only belong in M-mode
Diffstat (limited to 'isa/rv64mi')
-rw-r--r--isa/rv64mi/illegal.S40
-rw-r--r--isa/rv64mi/ma_addr.S84
2 files changed, 116 insertions, 8 deletions
diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S
index c5ccffd..ecb3088 100644
--- a/isa/rv64mi/illegal.S
+++ b/isa/rv64mi/illegal.S
@@ -1,8 +1,40 @@
# See LICENSE for license details.
+#*****************************************************************************
+# illegal.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal instruction trap.
+#
+
#include "riscv_test.h"
-#undef RVTEST_RV64S
-#define RVTEST_RV64S RVTEST_RV64M
-#define __MACHINE_MODE
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+ li TESTNUM, 2
+ .word 0
+ j fail
+
+ j pass
+
+ TEST_PASSFAIL
+
+mtvec_handler:
+ li t1, CAUSE_ILLEGAL_INSTRUCTION
+ csrr t0, mcause
+ bne t0, t1, fail
+ csrr t0, mepc
+ addi t0, t0, 8
+ csrw mepc, t0
+ sret
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
-#include "../rv64si/illegal.S"
+RVTEST_DATA_END
diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index 0448736..aa5dd85 100644
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -1,8 +1,84 @@
# See LICENSE for license details.
+#*****************************************************************************
+# ma_addr.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned ld/st trap.
+#
+
#include "riscv_test.h"
-#undef RVTEST_RV64S
-#define RVTEST_RV64S RVTEST_RV64M
-#define __MACHINE_MODE
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+ .align 3
+ auipc s0, 0
+
+ # indicate it's a load test
+ li s1, CAUSE_MISALIGNED_LOAD
+
+#define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \
+ li TESTNUM, testnum; \
+ insn x0, offset(base); \
+ j fail \
+
+ MISALIGNED_LDST_TEST(2, lh, s0, 1)
+ MISALIGNED_LDST_TEST(3, lhu, s0, 1)
+ MISALIGNED_LDST_TEST(4, lw, s0, 1)
+ MISALIGNED_LDST_TEST(5, lw, s0, 2)
+ MISALIGNED_LDST_TEST(6, lw, s0, 3)
+
+#ifdef __riscv64
+ MISALIGNED_LDST_TEST(7, lwu, s0, 1)
+ MISALIGNED_LDST_TEST(8, lwu, s0, 2)
+ MISALIGNED_LDST_TEST(9, lwu, s0, 3)
+
+ MISALIGNED_LDST_TEST(10, ld, s0, 1)
+ MISALIGNED_LDST_TEST(11, ld, s0, 2)
+ MISALIGNED_LDST_TEST(12, ld, s0, 3)
+ MISALIGNED_LDST_TEST(13, ld, s0, 4)
+ MISALIGNED_LDST_TEST(14, ld, s0, 5)
+ MISALIGNED_LDST_TEST(15, ld, s0, 6)
+ MISALIGNED_LDST_TEST(16, ld, s0, 7)
+#endif
+
+ # indicate it's a store test
+ li s1, CAUSE_MISALIGNED_STORE
+
+ MISALIGNED_LDST_TEST(22, sh, s0, 1)
+ MISALIGNED_LDST_TEST(23, sw, s0, 1)
+ MISALIGNED_LDST_TEST(24, sw, s0, 2)
+ MISALIGNED_LDST_TEST(25, sw, s0, 3)
+
+#ifdef __riscv64
+ MISALIGNED_LDST_TEST(26, sd, s0, 1)
+ MISALIGNED_LDST_TEST(27, sd, s0, 2)
+ MISALIGNED_LDST_TEST(28, sd, s0, 3)
+ MISALIGNED_LDST_TEST(29, sd, s0, 4)
+ MISALIGNED_LDST_TEST(30, sd, s0, 5)
+ MISALIGNED_LDST_TEST(31, sd, s0, 6)
+ MISALIGNED_LDST_TEST(32, sd, s0, 7)
+#endif
+
+ TEST_PASSFAIL
+
+ .align 3
+mtvec_handler:
+ csrr t0, mcause
+ bne t0, s1, fail
+
+ csrr t0, mepc
+ addi t0, t0, 8
+ csrw mepc, t0
+ sret
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
-#include "../rv64si/ma_addr.S"
+RVTEST_DATA_END