| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2024-05-30 | Support more basic testing of Zca instructions | Andrew Waterman | 1 | -13/+13 | |
| Continuation of fee361fd89edd4ac031a570affde16f4f84414e9 | |||||
| 2024-05-30 | Support basic testing of more Zca instructions | Andrew Waterman | 1 | -76/+76 | |
| By using Zca-friendly registers, we can reuse the existing tests to get quick-and-dirty coverage of Zca, when the assembler is told to use Zca. (This doesn't break non-Zca targets.) | |||||
| 2022-06-09 | Test misaligned stores. (#397) | Tim Newsome | 1 | -0/+15 | |
| Assume that misaligned loads work correctly. Passes `make -C isa run` against spike (both with and without misaligned support). | |||||
| 2022-06-07 | Test misaligned loads. | Tim Newsome | 1 | -0/+16 | |
| Cover lh, lw, and ld (only on rv64). | |||||
| 2022-06-07 | Set TESTNUM before executing code. | Tim Newsome | 1 | -1/+1 | |
| Tests that might cause a trap during their code need TESTNUM (gp) set so the trap handler can correctly identify which test is running, and also report that to the user in case the test fails. Fix up shamt.S and csr.S to handle the new behavior. | |||||
| 2022-06-06 | Revert unaligned tests. | Tim Newsome | 1 | -1/+1 | |
| They lead to two problems: 1. The change to set TESTNUM before the test instead of after broke a few tests that relied on the old behavior. 2. Some tests in the v variant do something in the exception handler such that when they get an unaligned access exception, they end up stuck in a loop of unaligned access exceptions and the exception handler set up in the test is never called. | |||||
| 2022-06-06 | Set TESTNUM before executing code. | Tim Newsome | 1 | -1/+1 | |
| Tests that might cause a trap during their code need TESTNUM (gp) set so the trap handler can correctly identify which test is running, and also report that to the user in case the test fails. | |||||
| 2020-11-11 | add zfh (float16) test case and related macros (#301) | Chih-Min Chao | 1 | -0/+73 | |
| * ext: add zfh extension test case and related macro Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * build: add zfh to target Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
| 2020-03-02 | enable rv32e compatability by replacing reg x29 with reg x7 (#250) | Cedric Orban | 1 | -12/+12 | |
| 2019-07-29 | Support RV32E. Fixed #198 (#200) | Leway Colin | 1 | -36/+36 | |
| 2017-11-26 | Rv32ud tests (#108) | Torbjørn | 1 | -0/+109 | |
| * Probably implemented the changes required to support fadd test for rv32ud * Created test files in rv32ud, implemented working(?) test for ldst * fclass, fcvt_w, fmin and recoding seem to be working now * Got fdiv (and sqrt) tests working * fmadd tests seem to work * fcmp works * [WIP] fcvt working, but lacks a 32-bit implementation of the final test * Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST * Added Makefrag for rv32ud tests and included in main isa Makefile * Don't run 64-bit tests if the defined XLEN is 32 | |||||
| 2017-03-21 | Avoid x3 (gp), which is now TESTNUM | Andrew Waterman | 1 | -30/+30 | |
| 2017-02-01 | Test FMIN/FMAX NaN behavior | Andrew Waterman | 1 | -0/+5 | |
| See https://github.com/riscv/riscv-isa-sim/issues/76 | |||||
| 2017-01-31 | Test qNaN and sNaN inputs to FP comparisons | Andrew Waterman | 1 | -4/+4 | |
| 2017-01-04 | Remove Hwacha macros | Andrew Waterman | 2 | -645/+0 | |
| 2017-01-04 | Mask off large constants for RV32 | Andrew Waterman | 1 | -23/+25 | |
| 2016-10-09 | Align FP data sections | Andrew Waterman | 1 | -12/+8 | |
| 2016-08-08 | move fclass macros into the same file as the rest (#22) | Colin Schmidt | 1 | -0/+8 | |
| 2016-07-29 | Add an RVC test | Andrew Waterman | 1 | -36/+0 | |
| 2016-04-30 | ERET -> xRET; new memory map | Andrew Waterman | 1 | -12/+12 | |
| For now, we no longer build hex files, because the programs don't start at address 0. This decision will likely be revisited. | |||||
| 2016-01-29 | Check NAN values in fdiv tests | Palmer Dabbelt | 1 | -0/+8 | |
| The new RISC-V ISA spec mandates NAN bit patterns. This test checks to make sure that those bit patterns come out of fsqrt(-1). These pass on both spike and Rocket. An additional _DWORD_RESULT version of the FP test macros is added to facilitate floating-point tests that compare against particular bit patterns. | |||||
| 2015-12-14 | change la to li as appropriate in test macros | Howard Mao | 1 | -2/+2 | |
| 2015-09-20 | Remove Hwacha v3 tests | Andrew Waterman | 1 | -123/+0 | |
| 2015-03-20 | Add fdiv test | Andrew Waterman | 1 | -4/+4 | |
| 2015-03-17 | relay hwacha cause/aux to scause/sbadaddr | Yunsup Lee | 1 | -4/+4 | |
| 2015-03-16 | revamp vector tests with new privileged spec, and add scalar pt tests | Yunsup Lee | 1 | -4/+2 | |
| 2015-03-12 | Update to new privileged spec | Andrew Waterman | 2 | -2/+2 | |
| 2015-01-09 | Add LICENSE | Andrew Waterman | 2 | -0/+4 | |
| 2015-01-04 | Avoid deprecated "b" pseudo-op; use "j" instead | Andrew Waterman | 2 | -6/+6 | |
| 2014-12-03 | Rely on assembler to relax far branches | Andrew Waterman | 1 | -12/+3 | |
| 2014-03-18 | Check FP corner cases and flags | Andrew Waterman | 2 | -30/+42 | |
| 2014-01-31 | Reference TESTNUM instead of x28 directly | Andrew Waterman | 2 | -51/+51 | |
| 2013-11-24 | Update to new privileged ISA | Andrew Waterman | 2 | -16/+20 | |
| 2013-11-05 | correctly set SR_EA bit for all vector physical tests | Yunsup Lee | 1 | -0/+2 | |
| 2013-10-17 | add hwacha exception support | Yunsup Lee | 1 | -19/+21 | |
| 2013-10-10 | revamp hwacha tests | Yunsup Lee | 2 | -44/+40 | |
| 2013-08-23 | Reflect changes to ISA | Andrew Waterman | 2 | -18/+18 | |
| Conflicts: isa/Makefile | |||||
| 2013-04-24 | add more header information to test_macros | Yunsup Lee | 2 | -183/+225 | |
| 2013-04-22 | initial commit | Yunsup Lee | 2 | -0/+1274 | |
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index : rocket-tools/riscv-tests.git | |
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