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| author | Tim Newsome <tim@sifive.com> | 2022-06-07 13:34:39 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-06-07 13:39:55 -0700 |
| commit | fb04a343df61c55849edc7734bc2a60d615fe49c (patch) | |
| tree | 0e6cebc9460b27150365077387fc4829729407fa /isa/macros | |
| parent | afef86516d1ec7289bae24e3ad247cca57e3fb3b (diff) | |
| download | riscv-tests-fb04a343df61c55849edc7734bc2a60d615fe49c.zip riscv-tests-fb04a343df61c55849edc7734bc2a60d615fe49c.tar.gz riscv-tests-fb04a343df61c55849edc7734bc2a60d615fe49c.tar.bz2 | |
Test misaligned loads.
Cover lh, lw, and ld (only on rv64).
Diffstat (limited to 'isa/macros')
| -rw-r--r-- | isa/macros/scalar/test_macros.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h index ee352e4..e286a44 100644 --- a/isa/macros/scalar/test_macros.h +++ b/isa/macros/scalar/test_macros.h @@ -217,6 +217,7 @@ test_ ## testnum: \ #define TEST_LD_OP( testnum, inst, result, offset, base ) \ TEST_CASE( testnum, x14, result, \ + li x15, result; /* Tell the exception handler the expected result. */ \ la x1, base; \ inst x14, offset(x1); \ ) @@ -701,6 +702,21 @@ test_ ## testnum: \ // ^ x14 is used in some other macros, to avoid issues we use x15 for upper word +#define MISALIGNED_LOAD_HANDLER \ + li t0, CAUSE_MISALIGNED_LOAD; \ + csrr t1, mcause; \ + bne t0, t1, fail; \ + \ + /* We got a misaligned exception. Pretend we handled it in software */ \ + /* by loading the correct result here. */ \ + mv a4, a5; \ + \ + /* And skip this instruction */ \ + csrr t0, mepc; \ + addi t0, t0, 4; \ + csrw mepc, t0; \ + mret + #----------------------------------------------------------------------- # Pass and fail code (assumes test num is in TESTNUM) #----------------------------------------------------------------------- |