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authorTim Newsome <tim@sifive.com>2022-06-09 15:31:21 -0700
committerGitHub <noreply@github.com>2022-06-09 15:31:21 -0700
commit71ee281ad5d2a09cf47234e4463379165f218a43 (patch)
treef31f5ca244cc2239d8eea9c9679a89f0c2feb76a /isa/macros
parentc73e991add1df5767dfb7092a067df6aec88b56f (diff)
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Test misaligned stores. (#397)
Assume that misaligned loads work correctly. Passes `make -C isa run` against spike (both with and without misaligned support).
Diffstat (limited to 'isa/macros')
-rw-r--r--isa/macros/scalar/test_macros.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h
index e286a44..6c901d0 100644
--- a/isa/macros/scalar/test_macros.h
+++ b/isa/macros/scalar/test_macros.h
@@ -226,8 +226,14 @@ test_ ## testnum: \
TEST_CASE( testnum, x14, result, \
la x1, base; \
li x2, result; \
+ la x15, 7f; /* Tell the exception handler how to skip this test. */ \
store_inst x2, offset(x1); \
load_inst x14, offset(x1); \
+ j 8f; \
+7: \
+ /* Set up the correct result for TEST_CASE(). */ \
+ mv x14, x2; \
+8: \
)
#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
@@ -717,6 +723,15 @@ test_ ## testnum: \
csrw mepc, t0; \
mret
+#define MISALIGNED_STORE_HANDLER \
+ li t0, CAUSE_MISALIGNED_STORE; \
+ csrr t1, mcause; \
+ bne t0, t1, fail; \
+ \
+ /* We got a misaligned exception. Skip this test. */ \
+ csrw mepc, x15; \
+ mret
+
#-----------------------------------------------------------------------
# Pass and fail code (assumes test num is in TESTNUM)
#-----------------------------------------------------------------------