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author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2015-03-16 02:10:17 -0700 |
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committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2015-03-16 02:10:17 -0700 |
commit | dd0d4036430dc812c9168fad8870d58ce151f498 (patch) | |
tree | 1e72637f1c2742de6a0e9bd6bd049d0215ce9b66 /isa/macros | |
parent | 62f8f78b5fc18e2f89e4b6429352ca4c980908c7 (diff) | |
download | riscv-tests-dd0d4036430dc812c9168fad8870d58ce151f498.zip riscv-tests-dd0d4036430dc812c9168fad8870d58ce151f498.tar.gz riscv-tests-dd0d4036430dc812c9168fad8870d58ce151f498.tar.bz2 |
revamp vector tests with new privileged spec, and add scalar pt tests
Diffstat (limited to 'isa/macros')
-rw-r--r-- | isa/macros/scalar/test_macros.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h index 81052a6..b4d0d78 100644 --- a/isa/macros/scalar/test_macros.h +++ b/isa/macros/scalar/test_macros.h @@ -570,9 +570,8 @@ test_ ## testnum: \ #----------------------------------------------------------------------- #define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \ - csrs status, SR_EI; \ la a0, handler ## testnum; \ - csrw evec, a0; \ + csrw stvec, a0; \ vsetcfg nxreg, nfreg; \ li a0, 4; \ vsetvl a0, a0; \ @@ -631,9 +630,8 @@ handler ## testnum: \ bne a1,a2,fail; \ #define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \ - csrs status, SR_EI; \ la a0, handler ## testnum; \ - csrw evec, a0; \ + csrw stvec, a0; \ vsetcfg nxreg, nfreg; \ li a0, 4; \ vsetvl a0, a0; \ |