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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-17 19:35:34 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-17 19:35:34 -0700 |
| commit | 2f00c0c1f26a10f93f4a133bec69f4d0b95df685 (patch) | |
| tree | 699ebd180e0de1076a2a511e5a2f133035dc8ca8 /isa/macros | |
| parent | ddf8212714fcb6dc240a71bd1e1f52e02fc208b0 (diff) | |
| download | riscv-tests-2f00c0c1f26a10f93f4a133bec69f4d0b95df685.zip riscv-tests-2f00c0c1f26a10f93f4a133bec69f4d0b95df685.tar.gz riscv-tests-2f00c0c1f26a10f93f4a133bec69f4d0b95df685.tar.bz2 | |
add hwacha exception support
Diffstat (limited to 'isa/macros')
| -rw-r--r-- | isa/macros/scalar/test_macros.h | 40 |
1 files changed, 21 insertions, 19 deletions
diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h index 7da0b59..b856701 100644 --- a/isa/macros/scalar/test_macros.h +++ b/isa/macros/scalar/test_macros.h @@ -559,10 +559,11 @@ test_ ## testnum: \ #----------------------------------------------------------------------- -# RV64UV MACROS +# RV64SV MACROS #----------------------------------------------------------------------- -#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \ +#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \ + setpcr status, SR_EI; \ la a0, handler ## testnum; \ mtpcr a0, evec; \ vsetcfg nxreg, nfreg; \ @@ -574,13 +575,14 @@ test_ ## testnum: \ vld vx3, a1; \ lui a0,%hi(vtcode1 ## testnum); \ vf %lo(vtcode1 ## testnum)(a0); \ + la reg2, dest; \ +illegal ## testnum: \ + inst reg1, reg2; \ la a3, dest; \ vsd vx2, a3; \ fence; \ vtcode1 ## testnum: \ add x2, x2, x3; \ -illegal ## testnum: \ - inst reg1, reg2, reg3; \ stop; \ vtcode2 ## testnum: \ add x2, x2, x3; \ @@ -588,12 +590,13 @@ vtcode2 ## testnum: \ handler ## testnum: \ vxcptkill; \ li x28,2; \ - mfpcr a0,cr6; \ - li a1,26; \ - bne a0,a1,fail; \ - mfpcr a0,cr2; \ - la a1,illegal ## testnum; \ + vxcptcause a0; \ + li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \ bne a0,a1,fail; \ + vxcptaux a0; \ + la a1, illegal ## testnum; \ + lw a2, 0(a1); \ + bne a0, a2, fail; \ vsetcfg 32,0; \ li a0,4; \ vsetvl a0,a0; \ @@ -620,7 +623,8 @@ handler ## testnum: \ li x28,5; \ bne a1,a2,fail; \ -#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, aux) \ +#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \ + setpcr status, SR_EI; \ la a0, handler ## testnum; \ mtpcr a0, evec; \ vsetcfg nxreg, nfreg; \ @@ -632,14 +636,13 @@ handler ## testnum: \ vld vx3, a1; \ lui a0,%hi(vtcode1 ## testnum); \ vf %lo(vtcode1 ## testnum)(a0); \ - la reg2, dest; \ -illegal ## testnum: \ - inst reg1, reg2; \ la a3, dest; \ vsd vx2, a3; \ fence; \ vtcode1 ## testnum: \ add x2, x2, x3; \ +illegal ## testnum: \ + inst reg1, reg2, reg3; \ stop; \ vtcode2 ## testnum: \ add x2, x2, x3; \ @@ -647,12 +650,12 @@ vtcode2 ## testnum: \ handler ## testnum: \ vxcptkill; \ li x28,2; \ - mfpcr a0,cr6; \ - li a1,27; \ + vxcptcause a0; \ + li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \ + bne a0,a1,fail; \ + vxcptaux a0; \ + la a1,illegal ## testnum; \ bne a0,a1,fail; \ - mfpcr a0, cr2; \ - li a1, aux; \ - bne a0, a1, fail; \ vsetcfg 32,0; \ li a0,4; \ vsetvl a0,a0; \ @@ -679,7 +682,6 @@ handler ## testnum: \ li x28,5; \ bne a1,a2,fail; \ - #----------------------------------------------------------------------- # Pass and fail code (assumes test num is in x28) #----------------------------------------------------------------------- |