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This is taking into account that the hardware limits count to 1.
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
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Make the non-existent csr configurable
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Signed-off-by: liangzhen <zhen.liang@spacemit.com>
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Signed-off-by: liangzhen <zhen.liang@spacemit.com>
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- Replace general "Exception" with "GdbServerError" in gdbserver.py for when no
samples are collected
- Replace general "Exception" with "TargetsException" in targets.py for XLEN
mismatch
- Introduce "TestLibError" exception in testlib.py and replace general
exceptions in various locations
- Update pylint.rc to remove overgeneral-exceptions warning
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`cease` is not a standard RISC-V extension, but is (was?) implemented in
Rocket, and also exists in some SiFive cores. It's useful to test
OpenOCD behavior when a hart becomes unavailable.
See also https://github.com/chipsalliance/rocket-chip/issues/1868
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Not as useful as I'd like because we don't connect until after examine()
has completed, and the test is likely to time out while debugging. But
good to have, and maybe I'll expand on it one day.
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* Another pylint upgrade.
Lots of format string changes, which are more readable.
More files to come...
* Satisfy pylint for two more files.
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I'm running a newer version of pylint, and thus there are new warnings
to be fixed. All very minor.
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* Test debugging multiple spikes in a daisy chain.
* Hugely speed up rbb_daisychain.
Now 2 dual-hart spikes are less than 4x slower than a single dual-hart
spike.
* WIP
* Test daisy chained homogeneous spike instances.
For OpenOCD, this means we're checking that we can talk to multiple
TAPs. Next up is heterogeneous testing.
* Enable Sv48Test.
Didn't mean to disable it with this commit.
* Test authentication again.
Another change I hadn't meant to push...
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* Add FreeRTOS smoke tests.
Make sure that OpenOCD can access all threads in a FreeRTOS binary on
single-hart RV32 and RV64.
* Also test `-rtos FreeRTOS`.
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This allows the vast majority of these tests to work with compilers that
don't support the V extension yet, which is helpful for people who
aren't using a vector branch of the compiler.
Specifically, this will hopefully allow us to run regression tests
against OpenOCD on every change, per
https://github.com/riscv/riscv-openocd/pull/563.
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HiFiveUnleashed-flash fails som address translation tests. Possibly that
would be fixed when https://github.com/riscv/riscv-tests/pull/313
merges.
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Make sure OpenOCD cooperates when a user sets a trigger by writing
tselect/tdata* directly.
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* WIP
* WIP
* Vector test seems to work well with spike.
* Check a0 in case the program didn't work right.
* Return not applicable if compile doesn't support V
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* Add a basic semihosting test.
* Need to configure semihosting on each target.
* WIP
* Parse "cannot insert breakpoint" message.
Also use sys.exit instead of exit, per new pylint's suggestion.
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The impetus for this was mostly that after my Ubuntu upgrade, pylint
suddenly starting to apply python3 rules, and I suppose it's time to
adopt python 3 now that it's been released for more than a decade.
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* Let the debugger enable mstatus.F if necessary.
* Ignore (some) gdb debug output.
* Increase timeout.
* Make newer version of pylint happy.
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Passes on spike and Arty. Won't merge until
https://github.com/riscv/riscv-openocd/pull/364 merges.
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Only works against spike, where I've implemented some custom debug
registers to test against.
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* Debug: Actually use the --32 and --64 command line arguments
* debug: make XLEN mismatch message clearer
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Fixes #83.
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The Gdb class now can handle connecting to more than one gdb. It
enumerates the harts across all connections, and when asked to select a
hart, it transparently sends future gdb commands to the correct
instance.
Multicore tests still have to be aware of some differences. The main one
is that when executing 'c' in RTOS mode, all harts resume, while in
multi-gdb mode only the current one resumes. Additionally, gdb doesn't
set breakpoints until 'c' is issued, so the hart where breakpoints are
set needs to be resumed before other harts might see them.
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Some boards have jumpers that control the reset vector, and forcing them
one way or another is more annoying than dealing with it in software.
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When compiling, define the number of harts. This means we only need to
allocate a lot of stack if there are a lot of harts.
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Targets now contain an array of harts. When running a regular test, one
hart is selected to run the test on while the remaining harts are parked
in a safe infinite loop.
There's currently only one test that tests multicore behavior, but there
could be more.
The infrastructure should be able to support heterogeneous multicore,
but I don't have a target like that to test with.
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I don't exactly understand why it has to be the way it is, but I just
want it to work.
Also fix a pylint complaint.
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files.
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Then for targets that can't handle this because they don't implement
hmode, add a target setting that allows that to be specified.
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I'm using this for a target where misa is at an old address, to
set riscv use_compressed_breakpoints off
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Instead of defining each target in targets.py, now each target gets its
own .py file. This means people can easily keep their own target files
around that they may not want to put into the main test source. As part
of that, I removed the freedom-u500-sim target since I assume it's only
used internally at SiFive.
Added a few cleanups as well:
* Update README examples, mostly --sim_cmd instead of --cmd.
* Allow defining misa in a target, to skip running of ExamineTarget.
* Rename target.target() to target.create(), which is less confusing.
* Default --sim_cmd to `spike`
* Got rid of `use_fpu`, instead looking at F or D in $misa.
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The spike64 target now links all test programs at 0x7fff_ffff_ffff_0000.
Also a minor change to log file naming so that 'make all' works again.
I'll fix this better later.
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If we want we can start using print(), but if so let's consistently use
it instead of piecemeal. See also
https://stackoverflow.com/questions/28694380/pylint-says-unnecessary-parens-after-r-keyword
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(actually it just gets an exception anyway).
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