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2023-10-24Support instruction count limit in IcountTestliangzhen1-0/+3
This is taking into account that the hardware limits count to 1. Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-17Merge pull request #513 from lz-bro/nonexist_csrTim Newsome1-0/+3
Make the non-existent csr configurable
2023-10-17Make the non-existent csr configurableliangzhen1-0/+3
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-10-16Make CLINT address configurableliangzhen1-1/+5
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
2023-07-17debug: Add support_unavailable_control property.Tim Newsome1-0/+3
2023-06-30Fix for https://github.com/riscv-software-src/riscv-tests/issues/482Tommy Murphy1-2/+2
2023-05-25debug: New pylint => new warnings => new cleanupsTim Newsome1-1/+4
- Replace general "Exception" with "GdbServerError" in gdbserver.py for when no samples are collected - Replace general "Exception" with "TargetsException" in targets.py for XLEN mismatch - Introduce "TestLibError" exception in testlib.py and replace general exceptions in various locations - Update pylint.rc to remove overgeneral-exceptions warning
2022-12-01debug: Park unused harts with a cease instruction. (#434)Tim Newsome1-0/+3
`cease` is not a standard RISC-V extension, but is (was?) implemented in Rocket, and also exists in some SiFive cores. It's useful to test OpenOCD behavior when a hart becomes unavailable. See also https://github.com/chipsalliance/rocket-chip/issues/1868
2022-10-07debug: Add --debug_server arg to open gdb on OpenOCDTim Newsome1-1/+5
Not as useful as I'd like because we don't connect until after examine() has completed, and the test is likely to time out while debugging. But good to have, and maybe I'll expand on it one day.
2022-06-23Another pylint upgrade. (#398)Tim Newsome1-20/+21
* Another pylint upgrade. Lots of format string changes, which are more readable. More files to come... * Satisfy pylint for two more files.
2022-05-31Address pylint warnings. (#385)Tim Newsome1-0/+1
I'm running a newer version of pylint, and thus there are new warnings to be fixed. All very minor.
2021-05-20Test multiple heterogeneous spike instances. (#338)Tim Newsome1-9/+16
2021-05-07Test daisy chained homogeneous spike instances. (#334)Tim Newsome1-0/+7
* Test debugging multiple spikes in a daisy chain. * Hugely speed up rbb_daisychain. Now 2 dual-hart spikes are less than 4x slower than a single dual-hart spike. * WIP * Test daisy chained homogeneous spike instances. For OpenOCD, this means we're checking that we can talk to multiple TAPs. Next up is heterogeneous testing. * Enable Sv48Test. Didn't mean to disable it with this commit. * Test authentication again. Another change I hadn't meant to push...
2021-04-13Add FreeRTOS smoke tests. (#333)Tim Newsome1-2/+7
* Add FreeRTOS smoke tests. Make sure that OpenOCD can access all threads in a FreeRTOS binary on single-hart RV32 and RV64. * Also test `-rtos FreeRTOS`.
2021-01-08Disable V extension when compiler doesn't support it. (#317)Tim Newsome1-2/+24
This allows the vast majority of these tests to work with compilers that don't support the V extension yet, which is helpful for people who aren't using a vector branch of the compiler. Specifically, this will hopefully allow us to run regression tests against OpenOCD on every change, per https://github.com/riscv/riscv-openocd/pull/563.
2020-12-31Make HiFiveUnleashed tests clean.Tim Newsome1-0/+4
HiFiveUnleashed-flash fails som address translation tests. Possibly that would be fixed when https://github.com/riscv/riscv-tests/pull/313 merges.
2020-12-14Add tests for memory sampling feature. (#300)Tim Newsome1-0/+4
2020-06-25Add manual hwbp test. (#283)Tim Newsome1-0/+4
Make sure OpenOCD cooperates when a user sets a trigger by writing tselect/tdata* directly.
2020-06-25Create a more sophisticated vector test (#284)Tim Newsome1-1/+1
* WIP * WIP * Vector test seems to work well with spike. * Check a0 in case the program didn't work right. * Return not applicable if compile doesn't support V
2020-05-26Test semihosting calls (#280)Tim Newsome1-0/+4
* Add a basic semihosting test. * Need to configure semihosting on each target. * WIP * Parse "cannot insert breakpoint" message. Also use sys.exit instead of exit, per new pylint's suggestion.
2020-03-05Add a simple mechanism to skip tests on targets. (#251)Tim Newsome1-0/+7
2019-11-22Move to Python 3. (#218)Tim Newsome1-3/+2
The impetus for this was mostly that after my Ubuntu upgrade, pylint suddenly starting to apply python3 rules, and I suppose it's time to adopt python 3 now that it's been released for more than a decade.
2019-08-02Miscellaneous minor test improvements (#199)Tim Newsome1-2/+1
* Let the debugger enable mstatus.F if necessary. * Ignore (some) gdb debug output. * Increase timeout. * Make newer version of pylint happy.
2019-07-15Make tests work with RV32E targets. (#196)Tim Newsome1-15/+27
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome1-0/+3
Passes on spike and Arty. Won't merge until https://github.com/riscv/riscv-openocd/pull/364 merges.
2018-11-14Cleanup and renamed test flag to invalid_memory_returns_zerocgsfv1-2/+2
2018-11-13Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fixcgsfv1-0/+3
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome1-0/+4
Only works against spike, where I've implemented some custom debug registers to test against.
2017-11-19Make pylint happy.Tim Newsome1-9/+11
2017-11-17debug: Fix the XLEN command line checkxlen_fixMegan Wachs1-7/+8
2017-11-16Debug: Use the --32 and --64 command line arguments (#97)Megan Wachs1-0/+5
* Debug: Actually use the --32 and --64 command line arguments * debug: make XLEN mismatch message clearer
2017-11-01Make pylint 1.6.5 happy.Tim Newsome1-1/+1
2017-10-12Pay attention to server_timeout_secTim Newsome1-2/+3
Fixes #83.
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome1-0/+2
The Gdb class now can handle connecting to more than one gdb. It enumerates the harts across all connections, and when asked to select a hart, it transparently sends future gdb commands to the correct instance. Multicore tests still have to be aware of some differences. The main one is that when executing 'c' in RTOS mode, all harts resume, while in multi-gdb mode only the current one resumes. Additionally, gdb doesn't set breakpoints until 'c' is issued, so the hart where breakpoints are set needs to be resumed before other harts might see them.
2017-09-19Allow multiple reset vectors.Tim Newsome1-0/+5
Some boards have jumpers that control the reset vector, and forcing them one way or another is more annoying than dealing with it in software.
2017-09-14Test debugging code with interrupts.Tim Newsome1-0/+3
2017-09-01Add some infrastructure for multicore tests.Tim Newsome1-29/+28
When compiling, define the number of harts. This means we only need to allocate a lot of stack if there are a lot of harts.
2017-08-28Make the debug tests aware of multicore.Tim Newsome1-61/+83
Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.
2017-08-14Put logfile code back so everything works again.Tim Newsome1-2/+2
I don't exactly understand why it has to be the way it is, but I just want it to work. Also fix a pylint complaint.
2017-08-14debug: Allow OpenOCD startup timeout to be specified. Print out path to log ↵Megan Wachs1-1/+8
files.
2017-07-20Add back code to clean up triggers in entry.STim Newsome1-0/+6
Then for targets that can't handle this because they don't implement hmode, add a target setting that allows that to be specified.
2017-07-03Add gdb_setup to target for arbitrary gdb commandsTim Newsome1-0/+4
I'm using this for a target where misa is at an old address, to set riscv use_compressed_breakpoints off
2017-06-26Move target definition into individual files.Tim Newsome1-111/+74
Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa.
2017-06-15Test 64-bit addressing.Tim Newsome1-7/+17
The spike64 target now links all test programs at 0x7fff_ffff_ffff_0000. Also a minor change to log file naming so that 'make all' works again. I'll fix this better later.
2017-06-05Make pylint happy.Tim Newsome1-1/+2
If we want we can start using print(), but if so let's consistently use it instead of piecemeal. See also https://stackoverflow.com/questions/28694380/pylint-says-unnecessary-parens-after-r-keyword
2017-05-18debug: Correct the calling for a 32-bit simulation targetMegan Wachs1-1/+1
2017-05-16Change Spike's RAM location to match the linker scriptPalmer Dabbelt1-2/+2
2017-05-15debug: Use consistent 'sim_cmd' argument.Megan Wachs1-1/+1
2017-04-18debug: Don't halt out of reset. It's unrealistic. Use a program which loops ↵Megan Wachs1-2/+2
(actually it just gets an exception anyway).
2017-04-17debug: Checkpoint restoring Spike functionalityMegan Wachs1-11/+11
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