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| author | Tim Newsome <tim@sifive.com> | 2022-12-01 10:30:33 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-12-01 10:30:33 -0800 |
| commit | 6a4225fae83a1ad9bf9687c13f1046baa401269e (patch) | |
| tree | d7dee754d1067ba3fbe856ea3c7434659a7e18fb /debug/targets.py | |
| parent | 068241464ee28131a811f70bd2a78e299e60af91 (diff) | |
| download | riscv-tests-6a4225fae83a1ad9bf9687c13f1046baa401269e.zip riscv-tests-6a4225fae83a1ad9bf9687c13f1046baa401269e.tar.gz riscv-tests-6a4225fae83a1ad9bf9687c13f1046baa401269e.tar.bz2 | |
debug: Park unused harts with a cease instruction. (#434)
`cease` is not a standard RISC-V extension, but is (was?) implemented in
Rocket, and also exists in some SiFive cores. It's useful to test
OpenOCD behavior when a hart becomes unavailable.
See also https://github.com/chipsalliance/rocket-chip/issues/1868
Diffstat (limited to 'debug/targets.py')
| -rw-r--r-- | debug/targets.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/debug/targets.py b/debug/targets.py index b2ed01b..ddd39d5 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -50,6 +50,9 @@ class Hart: # is fine. system = None + # Supports the cease instruction, which causes a hart to become unavailable. + support_cease = False + def __init__(self, misa=None, system=None, link_script_path=None): if misa: self.misa = misa |