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| author | Tim Newsome <tim@sifive.com> | 2023-10-17 09:52:14 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-10-17 09:52:14 -0700 |
| commit | d020e2069a9f6a9c0e875f23f0f4aababea9fbf0 (patch) | |
| tree | 9dd96b62245a9782be19da23dab818914d2d8174 /debug/targets.py | |
| parent | a176b65b40b9a2bcd5ce24334722036f82677eb5 (diff) | |
| parent | 57544c2c89f720015ca6c25ca1632603ab712901 (diff) | |
| download | riscv-tests-d020e2069a9f6a9c0e875f23f0f4aababea9fbf0.zip riscv-tests-d020e2069a9f6a9c0e875f23f0f4aababea9fbf0.tar.gz riscv-tests-d020e2069a9f6a9c0e875f23f0f4aababea9fbf0.tar.bz2 | |
Merge pull request #513 from lz-bro/nonexist_csr
Make the non-existent csr configurable
Diffstat (limited to 'debug/targets.py')
| -rw-r--r-- | debug/targets.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/debug/targets.py b/debug/targets.py index 081e2c6..189d79b 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -33,6 +33,9 @@ class Hart: # no device mapped to that location. bad_address = None + # The non-existent register for access test + nonexist_csr = "csr2288" + # Number of instruction triggers the hart supports. instruction_hardware_breakpoint_count = 0 |