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| author | liangzhen <zhen.liang@spacemit.com> | 2023-10-16 13:47:52 +0800 |
|---|---|---|
| committer | liangzhen <zhen.liang@spacemit.com> | 2023-10-16 13:47:52 +0800 |
| commit | 4dfd2e7b4b6ef3f1dc134d299cc2ea4d2bbadab1 (patch) | |
| tree | ba118d19cf517afb88cc6795b7937bd2f7777b94 /debug/targets.py | |
| parent | c36c814ae49610bc407a5c4e144866fa50e4510e (diff) | |
| download | riscv-tests-4dfd2e7b4b6ef3f1dc134d299cc2ea4d2bbadab1.zip riscv-tests-4dfd2e7b4b6ef3f1dc134d299cc2ea4d2bbadab1.tar.gz riscv-tests-4dfd2e7b4b6ef3f1dc134d299cc2ea4d2bbadab1.tar.bz2 | |
Make CLINT address configurable
Signed-off-by: liangzhen <zhen.liang@spacemit.com>
Diffstat (limited to 'debug/targets.py')
| -rw-r--r-- | debug/targets.py | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/debug/targets.py b/debug/targets.py index 3f63e79..081e2c6 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -93,9 +93,12 @@ class Target: # before starting the test. gdb_setup = [] - # Supports mtime at 0x2004000 + # Supports mtime default at clint_addr + 0x4000 supports_clint_mtime = True + # CLINT register address, set to the default value of spike. + clint_addr = 0x02000000 + # Implements custom debug registers like spike does. It seems unlikely any # hardware will every do that. implements_custom_test = False @@ -189,6 +192,7 @@ class Target: Target.temporary_files.append(self.temporary_binary) args = list(sources) + [ + f"-DCLINT={self.clint_addr}", "programs/entry.S", "programs/init.c", f"-DNHARTS={len(self.harts)}", "-I", "../env", |