diff options
| author | Megan Wachs <megan@sifive.com> | 2017-04-18 15:09:55 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2017-04-18 15:09:55 -0700 |
| commit | 2b116f9fb820641cb0a3a04e51164f2ef76478d6 (patch) | |
| tree | 3022795d926a051c6ee386ad832fc45b458b1b0d /debug/targets.py | |
| parent | b9cc9c27522499f91709d2ea6814692ed6131069 (diff) | |
| download | riscv-tests-2b116f9fb820641cb0a3a04e51164f2ef76478d6.zip riscv-tests-2b116f9fb820641cb0a3a04e51164f2ef76478d6.tar.gz riscv-tests-2b116f9fb820641cb0a3a04e51164f2ef76478d6.tar.bz2 | |
debug: Don't halt out of reset. It's unrealistic. Use a program which loops (actually it just gets an exception anyway).
Diffstat (limited to 'debug/targets.py')
| -rw-r--r-- | debug/targets.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/debug/targets.py b/debug/targets.py index d49b397..a69f43d 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -76,14 +76,14 @@ class Spike64Target(SpikeTarget): use_fpu = True def target(self): - return testlib.Spike(self.sim_cmd, halted=True) + return testlib.Spike(self.sim_cmd) class Spike32Target(SpikeTarget): name = "spike32" xlen = 32 def target(self): - return testlib.Spike(self.sim_cmd, halted=True, xlen=32) + return testlib.Spike(self.sim_cmd, xlen=32) class FreedomE300Target(Target): name = "freedom-e300" |