Age | Commit message (Collapse) | Author | Files | Lines |
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the load-acquire byte (so `lb.aq` and `lb.aqrl`), I'm not sure that will work but it passes the tests here.
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* add mop.r.N and mop.rr.N pseudo-inst
* add c.mop.N pseudo-inst
* add arg_lut entries and emitted pseudoops for Zimop/Zcmop
* add pseudoinsts for Zimop
* add pseudoinsts for Zcmop
* update zcmop mnemonics
* update zcmop mnemonics
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Remove unratified `Zvamo` instructions from `rv_v`
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If this is the only thing happening, I would have just moved those
instructions to unratified/rv_zvamo. The reason I didn't is, there is
the 'Zabha' extension (containing subword AMO instructions) in the fast
track and 8-bit vector AMO instructions conflict with it.
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Fix artifact generation
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rename rv_debug to rv_sdext
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split dret from rv_system to rv_debug
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Because neither priv and unpriv isa mentions dret, and debug is lived in
a standalone spec, move dret out from rv_system, while putting it into
rv_debug
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split arg_lut, causes, csr, csr32 from constants.py
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Remove duplicate zimm
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Signed-off-by: Jiuyang Liu <liu@jiuyang.me>
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retain the original shift instructions as pseudo-ops as well
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This is how its done in rv32_i as well.
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fix instruction duplication between rv128_c and rv64_c
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Generate compressed shift instructions for rv32
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C.ADDIW cannot have an rd of 0
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The non-compressed shift instructions have _rv32 versions. Do
the same for the compressed shift instructions.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
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The code point of rd=0 in C.ADDIW is restricted.
Fix formatting while in these files.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
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Add unratified Zimop and Zcmop extension instructions
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Svadu: Rename HADE to ADUE in *envcfg
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Add Smcntrpmf CSRs
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nrajovic/fix_vector_mask_register_logical_instructions
rv_v: fix for Vector Mask-Register Logical instructions.
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- resolves issue #180
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Adds mcyclecfg (0x321), minstrefcfg (0x322), mcyclecfgh (0x721),
minstretcfgh (0x722).
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Adds CSR scountinhibit (0x120), MSTATEEN0.CD (bit 56), and siselect
range (0x40 - 0x5F).
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Add Smcsrind/Sscsrind CSRs
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Adds mireg2 (0x352), mireg3 (0x353), mireg4 (0x355), mireg5 (0x356),
mireg6 (0x357), sireg2 (0x152), sireg3 (0x153), sireg4 (0x155), sireg5
(0x156), sireg6 (0x157), vsireg2 (0x252), vsireg3 (0x253), vsireg4
(0x255), vsireg5 (0x256), vireg6 (0x257).
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Update encodings for vfwmaccbf16.vv/vf
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Add (unratified) Zacas extension
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change decode generation part of chisel
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Support for Zvk, Vector Cryptography Extensions
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Add encodings for all instructions in the Zvk extensions:
- Zvbb, Vector Bit-manipulation instructions used in Cryptography,
- Zvbc, Vector Carryless Multiplication
- Zvkg, Vector GCM/GMAC instruction for Cryptography,
- Zvkned, NIST Suite: Vector AES Encryption & Decryption (Single
Round),
- Zvknha, Zvknhb, NIST Suite: Vector SHA-2,
- Zvksed, ShangMi Suite: SM4 Block Cipher Instructions
- Zvkssh, ShangMi Suite: SM3 Hash Function Instructions
Add two "shorthand" extensions:
- Zvkn: NIST Suite, imports Zvbb, Zvbc, Zvkned, and Zvknh
- Zvks: ShangMi Suite, imports Zvbb, Zvbc, Zvksed, and Zvksh
Three new fields are listed in constants.py:
- 'zimm5', used to encode round constants (Zvkns, Zvksed, Zvksh),
and 5-bit shift constant (vwsll.vi in Zvbb)
- 'zimm6hi, zimm6lo', used to encode the 6 bits rotate amount
in vror.vi.
The Zvk instructions – with the exception of Zvbb, Zvbc – reside in the
P opcode space. Some encodings conflict with proposed instructions
in the P extension (packed SIMD). Zvk and P are exclusive of each
other, no implementation will implement both. Conflicting P instructions
are marked as pseudo of the Zvk instructions.
The encodings match the current documentation of the specification
at <https://github.com/riscv/riscv-crypto/tree/master/doc/vector>,
at Version v0.9.1, 25 April, 2023 (Freeze Candidate).
Co-authored-by: Eric Gouriou <ego@rivosinc.com>
Co-authored-by: Stanislaw Kardach <kda@semihalf.com>
Co-authored-by: Kornel Duleba <mindal@semihalf.com>
Co-authored-by: Raghav Gupta <rgupta@rivosinc.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
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Add (unratified) BF16(Zfbfmin/Zvfbfmin/Zvfbfwma) extensions.
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Fix merging of instructions with the same name
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Fixes generation of 'extension' field for instr_dict.yaml
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