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2024-02-06Fix hvip.VSEIP and hvip.VSTIP, so they don't observe platform-specific interr...YenHaoChen1-10/+1
2024-01-11Fix vectored VS-level interruptsScott Johnson1-1/+1
2024-01-11Introduce adjusted_cause which I will reuse nextScott Johnson1-1/+2
2024-01-11Introduce interrupt_bit which I will reuse nextScott Johnson1-1/+2
2023-12-30Add srmcfg CSRVed Shanbhogue1-1/+7
2023-12-22typo: correct sstateen CSR addressYenHaoChen1-1/+1
2023-12-08Remove cfg_arg_t from cfg_tJerry Zhao1-1/+1
2023-12-07refactor: single statement of declaration and initialization on miselect, sis...YenHaoChen1-6/+3
2023-12-06miselect: support miselect when enabling smcsrindYenHaoChen1-0/+3
2023-11-04expose pmp granularity as a cli option.Karthik B K1-1/+1
2023-08-14rename *envcfg.HADE to *envcfg.ADUEVed Shanbhogue1-2/+2
2023-07-26Add Smcntrpmf functionalityAtul Khare1-2/+21
2023-07-26Add prv_changed / v_changed fields to stateAtul Khare1-0/+4
2023-07-25Merge pull request #1383 from rivosinc/sscrind_featureAndrew Waterman1-0/+40
2023-07-25legalize menvcfg.CBIEYenHaoChen1-1/+1
2023-07-19Add Smcsrind/Sscsrind supportAtul Khare1-0/+40
2023-07-11Remove dependency of isa_parser_t on extension_tJerry Zhao1-1/+1
2023-06-19Implement Zacas extension.Gianluca Guida1-0/+5
2023-05-26Fix check for extensionGianluca Guida1-1/+1
2023-05-26Use HAVE_INT128 instead of __SIZEOF_INT128__Gianluca Guida1-1/+1
2023-05-25Refactor set_privilege to subsume set_virtAndrew Waterman1-28/+7
2023-05-25Move setting of V=0 for M-mode trapScott Johnson1-1/+1
2023-05-25Move setting of V=0 for HS-mode trapScott Johnson1-1/+1
2023-05-25Explicitly use the nonvirtual S-mode CSRs when going to HS-modeScott Johnson1-12/+12
2023-05-25Force V=1 when going to VS-mode trap handlerScott Johnson1-0/+1
2023-05-25Prevent possibility of V=1 and PRV=M when entering debug modeAndrew Waterman1-0/+1
2023-05-25Implement dcsr.v and make DRET use itAndrew Waterman1-1/+1
2023-05-24Add prev_prv to processor stateAtul Khare1-1/+2
2023-05-24Add pre_v to processor stateAtul Khare1-12/+11
2023-05-11Use passed in virtual bit for creating traps in take_trigger_action() rahter ...rbuchner1-1/+1
2023-05-11Plumb in effective virtual bit to take_trigger_action()rbuchner1-1/+1
2023-04-11explicitly show D(-mode) instead of M(-mode) when in debug modeYenHaoChen1-0/+2
2023-04-04Decrement icount trigger count on external interruptScott Johnson1-0/+1
2023-03-29Support zihpm && !zicntrJerry Zhao1-2/+2
2023-03-29Set counteren_mask properly when !(zihpm && zicntr)Jerry Zhao1-1/+1
2023-03-20Implement Smrnmi extensionAndrew Waterman1-3/+16
2023-02-07Merge pull request #1245 from riscv-software-src/misa-c-writableAndrew Waterman1-2/+3
2023-02-06Make JVT CSR definition account for dynamically disabling ZcmtAndrew Waterman1-1/+1
2023-02-06Add infrastructure to dynamically disable multi-letter extensionsWeiwei Li1-1/+2
2023-02-06Use sv57 paging for rv64 configurationsJerry Zhao1-1/+1
2023-02-06Set cfg-provided processor_t.pmp_num before parsing the dtbJerry Zhao1-1/+1
2023-02-04Remove decode_macros.h from disasm.hJerry Zhao1-0/+1
2023-01-30triggers: force to slow path with icount triggersYenHaoChen1-1/+5
2023-01-27Enable Svadu control bits in menvcfg and henvcfgAaron Durbin1-0/+2
2023-01-19Improve PMP number/granularity error messagesAndrew Waterman1-3/+4
2023-01-18Instantiate tdata/tinfo as const csrs when trigger_count == 0Jerry Zhao1-5/+11
2023-01-18Add trigger_count field to cfg_tJerry Zhao1-1/+1
2023-01-03Fix debug-mode regression introduced by 20e7f53Jerry Zhao1-0/+2
2023-01-03Pass cfg object to processor_t constructorAndrew Waterman1-5/+4
2022-12-27Prevent processor_t from retiring instructions after a WFIJerry Zhao1-0/+4
generated by cgit v1.1 at 2024-08-18 08:07:30 +0000