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rocket-tools/riscv-isa-sim.git
confprec
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riscv
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processor.cc
Age
Commit message (
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Author
Files
Lines
2024-02-06
Fix hvip.VSEIP and hvip.VSTIP, so they don't observe platform-specific interr...
YenHaoChen
1
-10
/
+1
2024-01-11
Fix vectored VS-level interrupts
Scott Johnson
1
-1
/
+1
2024-01-11
Introduce adjusted_cause which I will reuse next
Scott Johnson
1
-1
/
+2
2024-01-11
Introduce interrupt_bit which I will reuse next
Scott Johnson
1
-1
/
+2
2023-12-30
Add srmcfg CSR
Ved Shanbhogue
1
-1
/
+7
2023-12-22
typo: correct sstateen CSR address
YenHaoChen
1
-1
/
+1
2023-12-08
Remove cfg_arg_t from cfg_t
Jerry Zhao
1
-1
/
+1
2023-12-07
refactor: single statement of declaration and initialization on miselect, sis...
YenHaoChen
1
-6
/
+3
2023-12-06
miselect: support miselect when enabling smcsrind
YenHaoChen
1
-0
/
+3
2023-11-04
expose pmp granularity as a cli option.
Karthik B K
1
-1
/
+1
2023-08-14
rename *envcfg.HADE to *envcfg.ADUE
Ved Shanbhogue
1
-2
/
+2
2023-07-26
Add Smcntrpmf functionality
Atul Khare
1
-2
/
+21
2023-07-26
Add prv_changed / v_changed fields to state
Atul Khare
1
-0
/
+4
2023-07-25
Merge pull request #1383 from rivosinc/sscrind_feature
Andrew Waterman
1
-0
/
+40
2023-07-25
legalize menvcfg.CBIE
YenHaoChen
1
-1
/
+1
2023-07-19
Add Smcsrind/Sscsrind support
Atul Khare
1
-0
/
+40
2023-07-11
Remove dependency of isa_parser_t on extension_t
Jerry Zhao
1
-1
/
+1
2023-06-19
Implement Zacas extension.
Gianluca Guida
1
-0
/
+5
2023-05-26
Fix check for extension
Gianluca Guida
1
-1
/
+1
2023-05-26
Use HAVE_INT128 instead of __SIZEOF_INT128__
Gianluca Guida
1
-1
/
+1
2023-05-25
Refactor set_privilege to subsume set_virt
Andrew Waterman
1
-28
/
+7
2023-05-25
Move setting of V=0 for M-mode trap
Scott Johnson
1
-1
/
+1
2023-05-25
Move setting of V=0 for HS-mode trap
Scott Johnson
1
-1
/
+1
2023-05-25
Explicitly use the nonvirtual S-mode CSRs when going to HS-mode
Scott Johnson
1
-12
/
+12
2023-05-25
Force V=1 when going to VS-mode trap handler
Scott Johnson
1
-0
/
+1
2023-05-25
Prevent possibility of V=1 and PRV=M when entering debug mode
Andrew Waterman
1
-0
/
+1
2023-05-25
Implement dcsr.v and make DRET use it
Andrew Waterman
1
-1
/
+1
2023-05-24
Add prev_prv to processor state
Atul Khare
1
-1
/
+2
2023-05-24
Add pre_v to processor state
Atul Khare
1
-12
/
+11
2023-05-11
Use passed in virtual bit for creating traps in take_trigger_action() rahter ...
rbuchner
1
-1
/
+1
2023-05-11
Plumb in effective virtual bit to take_trigger_action()
rbuchner
1
-1
/
+1
2023-04-11
explicitly show D(-mode) instead of M(-mode) when in debug mode
YenHaoChen
1
-0
/
+2
2023-04-04
Decrement icount trigger count on external interrupt
Scott Johnson
1
-0
/
+1
2023-03-29
Support zihpm && !zicntr
Jerry Zhao
1
-2
/
+2
2023-03-29
Set counteren_mask properly when !(zihpm && zicntr)
Jerry Zhao
1
-1
/
+1
2023-03-20
Implement Smrnmi extension
Andrew Waterman
1
-3
/
+16
2023-02-07
Merge pull request #1245 from riscv-software-src/misa-c-writable
Andrew Waterman
1
-2
/
+3
2023-02-06
Make JVT CSR definition account for dynamically disabling Zcmt
Andrew Waterman
1
-1
/
+1
2023-02-06
Add infrastructure to dynamically disable multi-letter extensions
Weiwei Li
1
-1
/
+2
2023-02-06
Use sv57 paging for rv64 configurations
Jerry Zhao
1
-1
/
+1
2023-02-06
Set cfg-provided processor_t.pmp_num before parsing the dtb
Jerry Zhao
1
-1
/
+1
2023-02-04
Remove decode_macros.h from disasm.h
Jerry Zhao
1
-0
/
+1
2023-01-30
triggers: force to slow path with icount triggers
YenHaoChen
1
-1
/
+5
2023-01-27
Enable Svadu control bits in menvcfg and henvcfg
Aaron Durbin
1
-0
/
+2
2023-01-19
Improve PMP number/granularity error messages
Andrew Waterman
1
-3
/
+4
2023-01-18
Instantiate tdata/tinfo as const csrs when trigger_count == 0
Jerry Zhao
1
-5
/
+11
2023-01-18
Add trigger_count field to cfg_t
Jerry Zhao
1
-1
/
+1
2023-01-03
Fix debug-mode regression introduced by 20e7f53
Jerry Zhao
1
-0
/
+2
2023-01-03
Pass cfg object to processor_t constructor
Andrew Waterman
1
-5
/
+4
2022-12-27
Prevent processor_t from retiring instructions after a WFI
Jerry Zhao
1
-0
/
+4
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