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2019-04-06fixing compilation errors on openbsdDinesh Thirumurthy1-0/+7
2019-04-06Fix PMP checks for partially-matching accesses (#270)Andrew Waterman2-8/+21
2019-04-06Add --dmi-rti and --abstract-rti to test OpenOCD.Tim Newsome6-36/+84
2019-04-03rvv: Fixed the following instructions. Based on the new macrosDave.Wen6-9/+9
2019-04-03rvv: Fixed the following instructions. Based on the new macrosDave.Wen15-15/+15
2019-04-03rvv: remove the redundant targetDave.Wen1-1/+0
2019-04-03decode: fix the VX and VIs' parameter typeDave.Wen1-34/+34
2019-04-03rvv: add missing instruction to makefileChih-Min Chao1-0/+108
2019-04-03rvv: fix some loop macro usageChih-Min Chao8-15/+15
2019-04-03rvv: fix vmulh*_vx.hChih-Min Chao2-4/+4
2019-04-03rvv: fix widing saturation bit conditionChih-Min Chao8-8/+8
2019-04-03rvv:add widing saturation instructionChih-Min Chao8-30/+284
2019-04-03rvv: add integer saturation helper functionChih-Min Chao2-0/+45
2019-04-02rvv: fix operaned using for wide instrucitonChih-Min Chao3-3/+3
2019-04-02rvv: add missing file to makefileChih-Min Chao1-0/+10
2019-04-02rvv: fix encoding namingChih-Min Chao1-18/+18
2019-04-02rvv: add wvmulsu.v[vx]Chih-Min Chao2-4/+26
2019-04-02rvv: inter: fix element offsetChih-Min Chao1-4/+4
2019-04-02rvv: support vector registers dumping under interactive modeDave.Wen2-0/+43
2019-04-02rvv: fix a typo of register nameDave.Wen1-1/+1
2019-04-01rvv: add vfsg[nx]_v[vf]Dave.Wen4-4/+48
2019-04-01rdd: add vfred[max|min|sum|osum]_vsDave.Wen4-25/+26
2019-04-01decode: add new macro for floating point reductionDave.Wen1-0/+12
2019-04-01rvv: add vsgt[u]_v[ix]Dave.Wen4-4/+4
2019-04-01rvv: add vfredosum_vs.hDave.Wen1-2/+17
2019-04-01rvv: add vred[and|or|xor]_vv, vredmax[u]_vv, vredmin[u]_vv, vredsum_vvDave.Wen8-16/+27
2019-04-01decode: macros improvementDave.Wen1-40/+90
2019-04-01rvv: add missing target in the riscv.mk.inDave.Wen1-7/+8
2019-03-31rvv: add VFUNARY1 instructionsDave.Wen1-0/+20
2019-03-31rvv: add VFUNARY0 instructionsDave.Wen1-0/+33
2019-03-31decode: add the human readable VFUNARY0/VFUNARY1/VMUNARY0 vs1 decodeDave.Wen1-0/+30
2019-03-31rvv: add vaadd_v[vxi] and vasub_[vx]Dave.Wen5-10/+135
2019-03-31rvv: add vsadd[u]_v[vxi] and vssub[u]_v[vx]Dave.Wen10-20/+49
2019-03-31rvv: add clip instructionsDave.Wen6-7/+13
2019-03-31rvv: add vnclip[u]_v[vxi]Dave.Wen6-12/+216
2019-03-31rvv: rewrite the vector destination for varies sewDave.Wen2-4/+55
2019-03-31rvv: add most of widering alu operationChih-Min Chao20-37/+67
2019-03-31rvv: decode: add helper macro for most widering instrucctionChih-Min Chao1-0/+21
2019-03-29rvv: add vsmul_v[vx]Dave.Wen2-3/+55
2019-03-29processor: for rounding mode and config access functionsDave.Wen2-0/+29
2019-03-28vsetvli: if rs1 = x0, then use maximum vector lengthDave.Wen3-5/+5
2019-03-28rvv: add macro for vector signed/unsigned extension for varies SEWDave.Wen1-0/+4
2019-03-28rvv: add missing vfsgn?_vf makefile entriesChih-Min Chao1-0/+3
2019-03-28rvv: fix vmerge[xi] operand use and apply V_CHECK_MASK macroChih-Min Chao2-21/+11
2019-03-28rvv: add vfmerge.vfChih-Min Chao1-2/+7
2019-03-28rvv: imple vmpopc_m.hChih-Min Chao1-5/+14
2019-03-28rvv: decode: add another mask checkChih-Min Chao1-1/+8
2019-03-28rvv: add vfg[et]_vf, vfl[et]_v[vf], vfne_v[vf]Dave.Wen8-11/+107
2019-03-28rvv: add vfeq_v[vf]Dave.Wen2-3/+27
2019-03-28rvv: add FLEN for floating point registers length in bitsDave.Wen1-4/+1
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