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author | Dave.Wen <dave.wen@sifive.com> | 2019-03-31 22:23:58 -0700 |
---|---|---|
committer | Dave.Wen <dave.wen@sifive.com> | 2019-03-31 22:31:09 -0700 |
commit | 3b8750cd28208796e004b029207758f18df16eb9 (patch) | |
tree | 38b7d81ea1fe8636aad4ee648d57dd147a387070 /riscv | |
parent | 2edd3d33d6b2af567e3a639ac3ad1b106beab8d5 (diff) | |
download | spike-3b8750cd28208796e004b029207758f18df16eb9.zip spike-3b8750cd28208796e004b029207758f18df16eb9.tar.gz spike-3b8750cd28208796e004b029207758f18df16eb9.tar.bz2 |
rvv: add vsadd[u]_v[vxi] and vssub[u]_v[vx]
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/insns/vsadd_vi.h | 7 | ||||
-rw-r--r-- | riscv/insns/vsadd_vv.h | 7 | ||||
-rw-r--r-- | riscv/insns/vsadd_vx.h | 7 | ||||
-rw-r--r-- | riscv/insns/vsaddu_vi.h | 7 | ||||
-rw-r--r-- | riscv/insns/vsaddu_vv.h | 6 | ||||
-rw-r--r-- | riscv/insns/vsaddu_vx.h | 7 | ||||
-rw-r--r-- | riscv/insns/vssub_vv.h | 7 | ||||
-rw-r--r-- | riscv/insns/vssub_vx.h | 7 | ||||
-rw-r--r-- | riscv/insns/vssubu_vv.h | 7 | ||||
-rw-r--r-- | riscv/insns/vssubu_vx.h | 7 |
10 files changed, 49 insertions, 20 deletions
diff --git a/riscv/insns/vsadd_vi.h b/riscv/insns/vsadd_vi.h index 05f73c0..d8573bf 100644 --- a/riscv/insns/vsadd_vi.h +++ b/riscv/insns/vsadd_vi.h @@ -1,5 +1,8 @@ -// vsadd +// vsadd: Saturating adds of signed integers VI_VI_LOOP ({ - // NOT IMPLEMENTED YET + int64_t result = simm5 + vs2; + if (result >= (int64_t)(2^(sew - 1))) + result = (2^(sew - 1)) - 1; + vd = result; }) diff --git a/riscv/insns/vsadd_vv.h b/riscv/insns/vsadd_vv.h index 3936e8c..51cbaa7 100644 --- a/riscv/insns/vsadd_vv.h +++ b/riscv/insns/vsadd_vv.h @@ -1,5 +1,8 @@ -// vsadd +// vsadd: Saturating adds of signed integers VI_VV_LOOP ({ - // NOT IMPLEMENTED YET + int64_t result = vs1 + vs2; + if (result >= (int64_t)(2^(sew - 1))) + result = (2^(sew - 1)) - 1; + vd = result; }) diff --git a/riscv/insns/vsadd_vx.h b/riscv/insns/vsadd_vx.h index 4e534be..5765124 100644 --- a/riscv/insns/vsadd_vx.h +++ b/riscv/insns/vsadd_vx.h @@ -1,5 +1,8 @@ -// vsadd +// vsadd: Saturating adds of signed integers VI_VX_LOOP ({ - // NOT IMPLEMENTED YET + int64_t result = rs1 + vs2; + if (result >= (int64_t)(2^(sew - 1))) + result = (2^(sew - 1)) - 1; + vd = result; }) diff --git a/riscv/insns/vsaddu_vi.h b/riscv/insns/vsaddu_vi.h index 9bfd46a..c550563 100644 --- a/riscv/insns/vsaddu_vi.h +++ b/riscv/insns/vsaddu_vi.h @@ -1,5 +1,8 @@ -// vsaddu +// vsaddu: Saturating adds of unsigned integers VI_VI_LOOP ({ - // NOT IMPLEMENTED YET + uint64_t result = simm5 + vs2; + if (result >= (uint64_t)(2^(sew - 1))) + result = (2^(sew - 1)) - 1; + vd = result; }) diff --git a/riscv/insns/vsaddu_vv.h b/riscv/insns/vsaddu_vv.h index de1fa8c..c0a2198 100644 --- a/riscv/insns/vsaddu_vv.h +++ b/riscv/insns/vsaddu_vv.h @@ -1,6 +1,8 @@ // vsaddu: Saturating adds of unsigned integers VI_VV_LOOP ({ - //unsigned sum = - // update vxsat + uint64_t result = vs1 + vs2; + if (result >= (uint64_t)(2^(sew - 1))) + result = (2^(sew - 1)) - 1; + vd = result; }) diff --git a/riscv/insns/vsaddu_vx.h b/riscv/insns/vsaddu_vx.h index f9d8c3e..289492f 100644 --- a/riscv/insns/vsaddu_vx.h +++ b/riscv/insns/vsaddu_vx.h @@ -1,5 +1,8 @@ -// vsaddu +// vsaddu: Saturating adds of unsigned integers VI_VX_LOOP ({ - // NOT IMPLEMENTED YET + uint64_t result = rs1 + vs2; + if (result >= (uint64_t)(2^(sew - 1))) + result = (2^(sew - 1)) - 1; + vd = result; }) diff --git a/riscv/insns/vssub_vv.h b/riscv/insns/vssub_vv.h index 00e4a46..28269f2 100644 --- a/riscv/insns/vssub_vv.h +++ b/riscv/insns/vssub_vv.h @@ -1,5 +1,8 @@ -// vssub +// vssub: Saturating subs of signed integers VI_VV_LOOP ({ - // NOT IMPLEMENTED YET + int64_t result = vs1 - vs2; + if (result >= (int64_t)(2^(sew - 1))) + result = (2^(sew - 1)) - 1; + vd = result; }) diff --git a/riscv/insns/vssub_vx.h b/riscv/insns/vssub_vx.h index 69463c1..25efd36 100644 --- a/riscv/insns/vssub_vx.h +++ b/riscv/insns/vssub_vx.h @@ -1,5 +1,8 @@ -// vssub +// vssub: Saturating subs of signed integers VI_VX_LOOP ({ - // NOT IMPLEMENTED YET + int64_t result = rs1 - vs2; + if (result >= (int64_t)(2^(sew - 1))) + result = (2^(sew - 1)) - 1; + vd = result; }) diff --git a/riscv/insns/vssubu_vv.h b/riscv/insns/vssubu_vv.h index f8597a2..b25d006 100644 --- a/riscv/insns/vssubu_vv.h +++ b/riscv/insns/vssubu_vv.h @@ -1,5 +1,8 @@ -// vssubu +// vssubu: Saturating subs of unsigned integers VI_VV_LOOP ({ - // NOT IMPLEMENTED YET + uint64_t result = vs1 - vs2; + if (result >= (uint64_t)(2^(sew - 1))) + result = (2^(sew - 1)) - 1; + vd = result; }) diff --git a/riscv/insns/vssubu_vx.h b/riscv/insns/vssubu_vx.h index 739650a..f51e49b 100644 --- a/riscv/insns/vssubu_vx.h +++ b/riscv/insns/vssubu_vx.h @@ -1,5 +1,8 @@ -// vssubu +// vssubu: Saturating subs of unsigned integers VI_VX_LOOP ({ - // NOT IMPLEMENTED YET + uint64_t result = rs1 - vs2; + if (result >= (uint64_t)(2^(sew - 1))) + result = (2^(sew - 1)) - 1; + vd = result; }) |